set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

2020-06-29 08:03:19 -07:00
parent d33916f1e0
commit a70562d386
8 changed files with 40 additions and 11 deletions
--- a/hw/rtl/libs/VX_generic_queue.v
+++ b/hw/rtl/libs/VX_generic_queue.v
@@ -3,7 +3,7 @@
 module VX_generic_queue #(
    parameter DATAW,
    parameter SIZE = 16,
-    parameter BUFFERED_OUTPUT = (SIZE > 8)
+    parameter BUFFERED_OUTPUT = 1
 ) ( 
    input  wire             clk,
    input  wire             reset,