set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

hw/rtl/VX_alu_unit.v

@@ -13,8 +13,8 @@ module VX_alu_unit (
     output reg [31:0]  alu_result,
     output reg         alu_stall
 );
-    localparam DIV_PIPELINE_LEN = 20;
-    localparam MUL_PIPELINE_LEN = 8;
+    localparam DIV_PIPELINE_LEN = 18;
+    localparam MUL_PIPELINE_LEN = 1;
 
     wire[31:0] div_result_unsigned;
     wire[31:0] div_result_signed;

hw/rtl/VX_config.vh

@@ -8,7 +8,7 @@
 `endif
 
 `ifndef NUM_CORES
-`define NUM_CORES 1
+`define NUM_CORES 4
 `endif
 
 `ifndef NUM_WARPS
@@ -52,7 +52,7 @@
 `endif
 
 `ifndef L2_ENABLE
-`define L2_ENABLE (`NUM_CORES > 2)
+`define L2_ENABLE 0
 `endif
 
 `ifndef L3_ENABLE

hw/rtl/libs/VX_generic_queue.v

@@ -3,7 +3,7 @@
 module VX_generic_queue #(
     parameter DATAW,
     parameter SIZE = 16,
-    parameter BUFFERED_OUTPUT = (SIZE > 8)
+    parameter BUFFERED_OUTPUT = 1
 ) ( 
     input  wire             clk,
     input  wire             reset,