Inefficient context aware desgin

rtl/VX_register_file.v

@@ -2,6 +2,7 @@
 
 module VX_register_file (
   input wire        clk,
+  input wire        in_warp,
   input wire        in_valid,
   input wire        in_write_register,
   input wire[4:0]   in_rd,
@@ -37,7 +38,7 @@ module VX_register_file (
 	assign write_enable   = (in_write_register && (in_rd != 5'h0)) && in_valid;
 
 	always @(posedge clk) begin
-		if(write_enable) begin
+		if(write_enable && in_warp) begin
 			// $display("RF: Writing %h to %d",write_data, write_register);
 			registers[write_register] <= write_data;
 		end