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Inefficient context aware desgin

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This commit is contained in:
felsabbagh3
2019-05-08 15:55:06 -07:00
parent 79356c7ab1
commit a6c13bc38c
21 changed files with 639 additions and 464 deletions
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3
rtl/VX_context.v
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@@ -3,6 +3,7 @@
module VX_context (
input wire clk,
input wire in_warp,
input wire in_valid[`NT_M1:0],
input wire in_write_register,
input wire[4:0] in_rd,
@@ -30,6 +31,7 @@ module VX_context (
VX_register_file vx_register_file_master(
.clk (clk),
.in_warp (in_warp),
.in_valid (in_valid[0]),
.in_write_register (in_write_register),
.in_rd (in_rd),
@@ -49,6 +51,7 @@ module VX_context (
assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_warp (in_warp),
.in_valid (in_valid[index]),
.in_write_register (in_write_register),
.in_rd (in_rd),