From a56ecb696d26e76570f6235a2d16dba4245fbf23 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 16 Jan 2021 14:05:47 -0800 Subject: [PATCH] minor updates --- hw/rtl/cache/VX_cache.v | 12 ++++++------ hw/rtl/cache/VX_shared_mem.v | 1 + 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index c4f2dbad..70981983 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -199,11 +199,11 @@ module VX_cache #( assign per_bank_core_req_ready[i] = curr_bank_core_req_ready; // Core WB - assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i]; - assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid; - assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid; - assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; - assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; + assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i]; + assign per_bank_core_rsp_valid[i] = curr_bank_core_rsp_valid; + assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid; + assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; + assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; // DRAM request assign per_bank_dram_req_valid[i] = curr_bank_dram_req_valid; @@ -232,7 +232,7 @@ module VX_cache #( .BANK_ID (i), .CACHE_ID (CACHE_ID), .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), + .CACHE_LINE_SIZE (CACHE_LINE_SIZE), .NUM_BANKS (NUM_BANKS), .WORD_SIZE (WORD_SIZE), .NUM_REQS (NUM_REQS), diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 22428ec9..42b55308 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -136,6 +136,7 @@ module VX_shared_mem #( VX_fifo_queue #( .DATAW (NUM_BANKS * (1 + `REQS_BITS + 1 + WORD_SIZE + `LINE_SELECT_BITS + `WORD_WIDTH + CORE_TAG_WIDTH)), .SIZE (CREQ_SIZE), + .BUFFERED (1), .FASTRAM (1) ) core_req_queue ( .clk (clk),