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Finished cache, dram imp + interfaces left

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This commit is contained in:
felsabbagh3
2020-03-03 19:42:33 -08:00
parent 8ece8d8893
commit a47f7c11ec
4 changed files with 329 additions and 38 deletions
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140
rtl/VX_cache/VX_bank.v
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@@ -119,6 +119,16 @@ module VX_bank (
wire [2:0] mrvq_mem_read_st0;
wire [2:0] mrvq_mem_write_st0;
wire miss_add;
wire[31:0] miss_add_addr;
wire[31:0] miss_add_data;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid;
wire[4:0] miss_add_rd;
wire[1:0] miss_add_wb;
wire[`NW_M1:0] miss_add_warp_num;
wire[2:0] miss_add_mem_read;
wire[2:0] miss_add_mem_write;
VX_cache_miss_resrv mrvq_queue(
.clk (clk),
.reset (reset),
@@ -151,16 +161,12 @@ module VX_bank (
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
);
wire stall_st0;
wire stall_st1;
wire stall_st2;
wire stall_bank_pipe;
assign stall_st1 = stall_st2;
assign stall_st0 = stall_st1;
assign dfpq_pop = !dfpq_empty && !stall_st0;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_st0;
assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_st0;
assign dfpq_pop = !dfpq_empty && !stall_bank_pipe;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe;
assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0];
wire qual_is_fill_st0;
@@ -191,14 +197,14 @@ module VX_bank (
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0, mrvq_wb_st0, mrvq_warp_num_st0, mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} :
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
0;
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall_st1),
.stall(stall_bank_pipe),
.flush(0),
.in ({qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
.out ({valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]})
@@ -210,8 +216,8 @@ module VX_bank (
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_st1),
.flush(is_fill_st1),
.stall(stall_bank_pipe),
.flush(0),
.in ({valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}),
.out ({valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] })
);
@@ -221,34 +227,122 @@ module VX_bank (
wire[31:0] readword_st1e;
wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e;
wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
wire [4:0] rd_st1e;
wire [1:0] wb_st1e;
wire [`NW_M1:0] warp_num_st1e;
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e;
assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1];
VX_tag_data_access VX_tag_data_access(
.clk (clk),
.reset (reset),
.valid_st10 (valid_st10),
.stall (stall),
// Read start
// Initial Read
.readaddr_st10 (addr_st1[0]),
// Write stuff
// Actual Read/Write
.valid_req_st1e(valid_st1[`STAGE_1_CYCLES-1]),
.writefill_st1e(is_fill_st1[`STAGE_1_CYCLES-1]),
.writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]),
.writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e), // TODO
.writedata_st1e(writedata_st1[`STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e),
.mem_read_st1e (mem_read_st1e),
// Fill info
.is_fill_st1e (is_fill_st1[`STAGE_1_CYCLES-1]),
.filldata_st1e (writedata_st1[`STAGE_1_CYCLES-1]),
// Read stuff + result
.mem_read_st1e (mem_read_st1e), // TODO
// Read Data
.readword_st1e (readword_st1e),
.readdata_st1e (readdata_st1e),
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e)
);
wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1];
wire valid_st2;
wire[31:0] addr_st2;
wire[31:0] writeword_st2;
wire[31:0] readword_st2;
wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
VX_generic_register #(.N( 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}),
.out ({valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && miss_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;
assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
// Enqueue to CWB Queue
wire cwbq_push = valid_st2 && !miss_st2;
wire [31:0] cwbq_data = readword_st2;
wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
wire [1:0] cwbq_wb = miss_add_wb;
wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
wire cwbq_full;
wire cwbq_empty;
VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
.push (cwbq_push),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data}),
.pop (bank_wb_pop),
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data}),
.empty (cwbq_empty),
.full (cwbq_full)
);
// Enqueue to DWB Queue
wire dwbq_push = valid_st2 && miss_st2 && dirty_st2;
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]}
wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
wire dwbq_full;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),
.push (dwbq_push),
.in_data ({dwbq_req_addr, dwbq_req_data}),
.pop (dram_wb_queue_pop),
.out_data({dram_wb_req_addr, dram_wb_req_data}),
.empty (dwbq_empty),
.full (dwbq_full)
);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full);
endmodule