Adding Vortex Yosys build support

hw/rtl/VX_platform.vh

@@ -9,6 +9,7 @@
 
 ///////////////////////////////////////////////////////////////////////////////
 
+`ifndef SYNTHESIS
 `ifndef NDEBUG
     `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
                            x \
@@ -47,8 +48,6 @@
                        . x () \
                        /* verilator lint_on PINCONNECTEMPTY */
 
-`define STRINGIFY(x) `"x`"
-
 `define STATIC_ASSERT(cond, msg) \
     generate                     \
         if (!(cond)) $error msg; \
@@ -60,24 +59,39 @@
 
 `define TRACING_ON  /* verilator tracing_on */
 `define TRACING_OFF /* verilator tracing_off */
-
+`else // SYNTHESIS
-`define RESET_RELAY(signal) \
+`define DEBUG_BLOCK(x)
-    wire signal;            \
+`define IGNORE_UNUSED_BEGIN
-    VX_reset_relay __``signal ( \
+`define IGNORE_UNUSED_END
-        .clk     (clk),     \
+`define IGNORE_WARNINGS_BEGIN
-        .reset   (reset),   \
+`define IGNORE_WARNINGS_END
-        .reset_o (signal)   \
+`define UNUSED_PARAM(x)
-    )
+`define UNUSED_VAR(x)
+`define UNUSED_PIN(x) . x ()
+`define STATIC_ASSERT(cond, msg)
+`define RUNTIME_ASSERT(cond, msg)
+`define TRACING_ON
+`define TRACING_OFF
+`endif // SYNTHESIS
 
 ///////////////////////////////////////////////////////////////////////////////
 
+`ifdef QUARTUS
 `define USE_FAST_BRAM   (* ramstyle = "MLAB, no_rw_check" *)
 `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
 `define DISABLE_BRAM    (* ramstyle = "logic" *)
 `define PRESERVE_REG    (* preserve *)
+`else
+`define USE_FAST_BRAM
+`define NO_RW_RAM_CHECK
+`define DISABLE_BRAM
+`define PRESERVE_REG
+`endif
 
 ///////////////////////////////////////////////////////////////////////////////
 
+`define STRINGIFY(x) `"x`"
+
 `define CLOG2(x)    $clog2(x)
 `define FLOG2(x)    ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0))
 `define LOG2UP(x)   (((x) > 1) ? $clog2(x) : 1)
@@ -117,4 +131,12 @@
     end                                         \
     dpi_trace("}")
 
+`define RESET_RELAY(signal) \
+    wire signal;            \
+    VX_reset_relay __``signal ( \
+        .clk     (clk),     \
+        .reset   (reset),   \
+        .reset_o (signal)   \
+    )
+
 `endif

hw/rtl/libs/VX_multiplier.v

@@ -49,15 +49,18 @@ module VX_multiplier #(
         assign result = result_unqual;
     end else begin        
         reg [WIDTHP-1:0] result_pipe [LATENCY-1:0];
-
+        always @(posedge clk) begin
-        for (genvar i = 0; i < LATENCY; i++) begin
+            if (enable) begin
+                result_pipe[0] <= result_unqual;
+            end
+        end
+        for (genvar i = 1; i < LATENCY; i++) begin
             always @(posedge clk) begin
                 if (enable) begin
-                    result_pipe[i] <= (0 == i) ? result_unqual : result_pipe[i-1];
+                    result_pipe[i] <= result_pipe[i-1];
                 end
             end
-        end        
+        end
-
         assign result = result_pipe[LATENCY-1]; 
     end
 

hw/syn/quartus/vortex/Makefile

@@ -1,6 +1,6 @@
 PROJECT = Vortex
 TOP_LEVEL_ENTITY = Vortex
-SRC_FILE = Vortex.sv
+SRC_FILE = Vortex.v
 RTL_DIR = ../../../../rtl
 
 FAMILY = "Arria 10"

hw/syn/yosys/Makefile

@@ -0,0 +1,17 @@
+PROJECT = Vortex
+TOP_LEVEL_ENTITY = Vortex
+SRC_FILE = Vortex.v
+RTL_DIR = ../../rtl
+
+DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2
+
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache
+
+# Build targets
+all: build
+
+build:
+	./synth.sh -t$(TOP_LEVEL_ENTITY) -s$(SRC_FILE) $(DEFINES) $(RTL_INCLUDE)
+
+clean:
+	rm -rf sources.v *.ys *.log

hw/syn/yosys/synth.sh

@@ -1,24 +1,67 @@
 #!/bin/bash
 
-dir_list='../../rtl/libs ../../rtl/cache ../../rtl/interfaces ../../rtl'
+# this script uses sv2v and yosys tools to run.
+# sv2v: https://github.com/zachjs/sv2v
+# yosys: http://www.clifford.at/yosys/
 
+# exit when any command fails
+set -e
+
+source=""
+top_level=""
+dir_list=()
+defines=""
+
+usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
+[ $# -eq 0 ] && usage
+while getopts "hs:t:I:D:" arg; do
+    case $arg in
+    s) # source
+        source=${OPTARG}
+        ;;
+    t) # top-level
+        top_level=${OPTARG}
+        ;;
+    I) # include directory
+        dir_list+=(${OPTARG})
+        ;;
+    D) # macro definition
+        defines="$defines -D${OPTARG}"
+        ;;
+    h | *) 
+      usage
+      exit 0
+      ;;
+  esac
+done
+
+echo "top_level=$top_level, source=$source, defines=$defines"
+
+# process include paths
 inc_list=""
-for dir in $dir_list; do
+for dir in "${dir_list[@]}" 
+do
+    echo "include: $dir" >> synth.log
 	inc_list="$inc_list -I$dir"
 done
 
-echo "inc_list=$inc_list"
+# process source files
+file_list=""
+for dir in "${dir_list[@]}" 
+do
+    for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) 
+    do
+        echo "file: $file" >> synth.log
+        file_list="$file_list $file"
+    done
+done
+
+# system-verilog to verilog conversion
+sv2v $defines -w output.v $inc_list $file_list
 
 {
-    # read design sources
+    echo "read_verilog -sv output.v"
-    for dir in $dir_list; do
+    echo "hierarchy -check -top $top_level"
-        for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) 
-        do
-            echo "read_verilog -sv $inc_list $file"
-        done
-    done
-
-    echo "hierarchy -check -top Vortex"
 
     # insertation of global reset
 	echo "add -global_input reset 1"
@@ -29,4 +72,4 @@ echo "inc_list=$inc_list"
     echo "write_verilog -noexpr -noattr synth.v"
 } > synth.ys
 
-yosys -l synth.log synth.ys
+yosys -l yosys.log synth.ys

hw/syn/yosys/synth.ys

@@ -1,99 +0,0 @@
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_bypass_buffer.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_cam_buffer.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_countones.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_divide.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_elastic_buffer.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fair_arbiter.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fixed_arbiter.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_queue.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_register.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_index_queue.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_matrix_arbiter.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_multiplier.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_onehot_encooder.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_priority_encoder.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_rr_arbiter.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_scope.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_serial_div.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_shift_register.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_skid_buffer.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank_core_req_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_req_bank_sel.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_rsp_merge.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_fill_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_req_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_miss_resrv.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_forwarder.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_rsp_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_access.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_store.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_alu_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_branch_ctl_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_rsp_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_rsp_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_rsp_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cmt_to_csr_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_rsp_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_to_issue_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_decode_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_exu_to_cmt_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_fpu_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_fpu_to_cmt_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_fpu_to_csr_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_rsp_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpu_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_ifetch_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_ifetch_rsp_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_join_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_lsu_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_mul_req_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_warp_ctl_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_writeback_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wstall_if.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_alu_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_cluster.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_commit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_core.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_data.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_io_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_dcache_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_decode.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_execute.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_fetch.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_fpu_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_bypass.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_fp_ctrl.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_ram.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_stage.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpu_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_ibuffer.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_icache_stage.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_instr_demux.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_io_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_ipdom_stack.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_issue.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_lsu_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_arb.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mul_unit.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_pipeline.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_scoreboard.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_warp_sched.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_writeback.v
-read_verilog -sv  -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/Vortex.v
-hierarchy -check -top Vortex
-add -global_input reset 1
-proc -global_arst reset
-synth -run coarse; opt -fine
-tee -o brams.log memory_bram -rules scripts/brams.txt;;
-write_verilog -noexpr -noattr synth.v