code refactoring for Vivado compatibility

2021-09-29 03:24:17 -04:00
parent 18c1dc2f0e
commit a45261b530
31 changed files with 133 additions and 110 deletions
--- a/hw/rtl/libs/VX_dp_ram.v
+++ b/hw/rtl/libs/VX_dp_ram.v
@@ -34,7 +34,7 @@ module VX_dp_ram #(
        end                                       \
    end

-`ifdef SYNTHESIS
+`ifdef __SYNTHESIS__
    if (LUTRAM) begin
        if (OUT_REG) begin        
            reg [DATAW-1:0] rdata_r;