code refactoring for Vivado compatibility

hw/rtl/libs/VX_bypass_buffer.v

@@ -31,7 +31,7 @@ module VX_bypass_buffer #(
                     buffer_valid <= 0;
                 end
                 if (valid_in && ~ready_out) begin
-                    `ASSERT(!buffer_valid, "runtime error");
+                    `ASSERT(!buffer_valid, ("runtime error"));
                     buffer_valid <= 1;
                 end
             end

hw/rtl/libs/VX_dp_ram.v

@@ -34,7 +34,7 @@ module VX_dp_ram #(
         end                                       \
     end
 
-`ifdef SYNTHESIS
+`ifdef __SYNTHESIS__
     if (LUTRAM) begin
         if (OUT_REG) begin        
             reg [DATAW-1:0] rdata_r;

hw/rtl/libs/VX_sp_ram.v

@@ -33,7 +33,7 @@ module VX_sp_ram #(
         end                                       \
     end
 
-`ifdef SYNTHESIS
+`ifdef __SYNTHESIS__
     if (LUTRAM) begin
         if (OUT_REG) begin        
             reg [DATAW-1:0] rdata_r;

hw/rtl/libs/VX_stream_arbiter.v

@@ -95,7 +95,7 @@ module VX_stream_arbiter #(
                 .grant_onehot (sel_onehot)
             );
         end else begin
-            $error ("invalid parameter");
+            `ERROR(("invalid parameter"));
         end
 
         wire [LANES-1:0] valid_in_sel;