code refactoring for Vivado compatibility

2021-09-29 03:24:17 -04:00
parent 18c1dc2f0e
commit a45261b530
31 changed files with 133 additions and 110 deletions
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -303,7 +303,7 @@ module VX_lsu_unit #(
    `SCOPE_ASSIGN (dcache_rsp_data,  dcache_rsp_if.data);
    `SCOPE_ASSIGN (dcache_rsp_tag,   mbuf_raddr);

-`ifndef SYNTHESIS
+`ifndef __SYNTHESIS__
    reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs;
    wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));