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Using verilog For-loops + Passing all tests

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This commit is contained in:
felsabbagh3
2019-03-30 22:09:03 -04:00
parent 99a0792a0c
commit a3a3b21de7
17 changed files with 1204 additions and 984 deletions
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58
rtl/Vortex.v
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@@ -5,8 +5,9 @@ module Vortex(
input wire clk,
input wire reset,
input wire[31:0] fe_instruction,
input wire[31:0] in_cache_driver_out_data_0,
input wire[31:0] in_cache_driver_out_data_1,
// input wire[31:0] in_cache_driver_out_data_0,
// input wire[31:0] in_cache_driver_out_data_1,
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
output wire[31:0] curr_PC,
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read,
@@ -15,10 +16,10 @@ module Vortex(
output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
);
wire[31:0] in_cache_driver_out_data[`NT_M1:0];
// wire[31:0] in_cache_driver_out_data[`NT_M1:0];
assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0;
assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
// assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0;
// assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
assign curr_PC = fetch_curr_PC;
@@ -42,7 +43,8 @@ wire[31:0] decode_csr_mask;
wire[4:0] decode_rd;
wire[4:0] decode_rs1;
wire[4:0] decode_rs2;
wire[31:0] decode_reg_data[`NT_T2_M1:0];
wire[31:0] decode_a_reg_data[`NT_M1:0];
wire[31:0] decode_b_reg_data[`NT_M1:0];
wire[1:0] decode_wb;
wire[4:0] decode_alu_op;
wire decode_rs2_src;
@@ -63,7 +65,8 @@ wire[31:0] d_e_csr_mask;
wire[4:0] d_e_rd;
wire[4:0] d_e_rs1;
wire[4:0] d_e_rs2;
wire[31:0] d_e_reg_data[`NT_T2_M1:0];
wire[31:0] d_e_a_reg_data[`NT_M1:0];
wire[31:0] d_e_b_reg_data[`NT_M1:0];
wire[4:0] d_e_alu_op;
wire[1:0] d_e_wb;
wire d_e_rs2_src;
@@ -89,14 +92,15 @@ wire[4:0] execute_rd;
wire[1:0] execute_wb;
wire[4:0] execute_rs1;
wire[4:0] execute_rs2;
wire[31:0] execute_reg_data[`NT_T2_M1:0];
wire[31:0] execute_a_reg_data[`NT_M1:0];
wire[31:0] execute_b_reg_data[`NT_M1:0];
wire[2:0] execute_mem_read;
wire[2:0] execute_mem_write;
wire execute_jal;
wire[31:0] execute_jal_dest;
wire[31:0] execute_branch_offset;
wire[31:0] execute_PC_next;
wire execute_valid[`NT_M1:0];
wire execute_valid[`NT_M1:0];
// From e_m_register
@@ -110,8 +114,9 @@ wire[4:0] e_m_rd;
wire[1:0] e_m_wb;
wire[4:0] e_m_rs1;
/* verilator lint_off UNUSED */
wire[31:0] e_m_reg_data[`NT_T2_M1:0];
wire[31:0] e_m_a_reg_data[`NT_M1:0];
/* verilator lint_on UNUSED */
wire[31:0] e_m_b_reg_data[`NT_M1:0];
wire[4:0] e_m_rs2;
wire[2:0] e_m_mem_read;
wire[2:0] e_m_mem_write;
@@ -119,7 +124,7 @@ wire[31:0] e_m_curr_PC;
wire[31:0] e_m_branch_offset;
wire[2:0] e_m_branch_type;
wire[31:0] e_m_PC_next;
wire e_m_valid[`NT_M1:0];
wire e_m_valid[`NT_M1:0];
// From memory
@@ -133,7 +138,7 @@ wire[1:0] memory_wb;
wire[4:0] memory_rs1;
wire[4:0] memory_rs2;
wire[31:0] memory_PC_next;
wire memory_valid[`NT_M1:0];
wire memory_valid[`NT_M1:0];
// From m_w_register
wire[31:0] m_w_alu_result[`NT_M1:0];
@@ -235,7 +240,8 @@ VX_decode vx_decode(
.out_rd (decode_rd),
.out_rs1 (decode_rs1),
.out_rs2 (decode_rs2),
.out_reg_data (decode_reg_data),
.out_a_reg_data (decode_a_reg_data),
.out_b_reg_data (decode_b_reg_data),
.out_wb (decode_wb),
.out_alu_op (decode_alu_op),
.out_rs2_src (decode_rs2_src),
@@ -257,7 +263,8 @@ VX_d_e_reg vx_d_e_reg(
.in_rd (decode_rd),
.in_rs1 (decode_rs1),
.in_rs2 (decode_rs2),
.in_reg_data (decode_reg_data),
.in_a_reg_data (decode_a_reg_data),
.in_b_reg_data (decode_b_reg_data),
.in_alu_op (decode_alu_op),
.in_wb (decode_wb),
.in_rs2_src (decode_rs2_src),
@@ -284,7 +291,8 @@ VX_d_e_reg vx_d_e_reg(
.out_rd (d_e_rd),
.out_rs1 (d_e_rs1),
.out_rs2 (d_e_rs2),
.out_reg_data (d_e_reg_data),
.out_a_reg_data (d_e_a_reg_data),
.out_b_reg_data (d_e_b_reg_data),
.out_alu_op (d_e_alu_op),
.out_wb (d_e_wb),
.out_rs2_src (d_e_rs2_src),
@@ -304,7 +312,8 @@ VX_execute vx_execute(
.in_rd (d_e_rd),
.in_rs1 (d_e_rs1),
.in_rs2 (d_e_rs2),
.in_reg_data (d_e_reg_data),
.in_a_reg_data (d_e_a_reg_data),
.in_b_reg_data (d_e_b_reg_data),
.in_alu_op (d_e_alu_op),
.in_wb (d_e_wb),
.in_rs2_src (d_e_rs2_src),
@@ -331,7 +340,8 @@ VX_execute vx_execute(
.out_wb (execute_wb),
.out_rs1 (execute_rs1),
.out_rs2 (execute_rs2),
.out_reg_data (execute_reg_data),
.out_a_reg_data (execute_a_reg_data),
.out_b_reg_data (execute_b_reg_data),
.out_mem_read (execute_mem_read),
.out_mem_write (execute_mem_write),
.out_jal (execute_jal),
@@ -349,7 +359,8 @@ VX_e_m_reg vx_e_m_reg(
.in_wb (execute_wb),
.in_rs1 (execute_rs1),
.in_rs2 (execute_rs2),
.in_reg_data (execute_reg_data),
.in_a_reg_data (execute_a_reg_data),
.in_b_reg_data (execute_b_reg_data),
.in_mem_read (execute_mem_read),
.in_mem_write (execute_mem_write),
.in_PC_next (execute_PC_next),
@@ -372,7 +383,8 @@ VX_e_m_reg vx_e_m_reg(
.out_wb (e_m_wb),
.out_rs1 (e_m_rs1),
.out_rs2 (e_m_rs2),
.out_reg_data (e_m_reg_data),
.out_a_reg_data (e_m_a_reg_data),
.out_b_reg_data (e_m_b_reg_data),
.out_mem_read (e_m_mem_read),
.out_mem_write (e_m_mem_write),
.out_curr_PC (e_m_curr_PC),
@@ -384,10 +396,10 @@ VX_e_m_reg vx_e_m_reg(
.out_valid (e_m_valid)
);
wire[31:0] use_rd2[`NT_M1:0];
// wire[31:0] use_rd2[`NT_M1:0];
assign use_rd2[0] = e_m_reg_data[1];
assign use_rd2[1] = e_m_reg_data[3];
// assign use_rd2[0] = e_m_reg_data[1];
// assign use_rd2[1] = e_m_reg_data[3];
VX_memory vx_memory(
.in_alu_result (e_m_alu_result),
@@ -397,7 +409,7 @@ VX_memory vx_memory(
.in_wb (e_m_wb),
.in_rs1 (e_m_rs1),
.in_rs2 (e_m_rs2),
.in_rd2 (use_rd2),
.in_rd2 (e_m_b_reg_data),
.in_PC_next (e_m_PC_next),
.in_curr_PC (e_m_curr_PC),
.in_branch_offset (e_m_branch_offset),