reset networks optimization
This commit is contained in:
13
hw/rtl/cache/VX_bank_core_req_arb.v
vendored
13
hw/rtl/cache/VX_bank_core_req_arb.v
vendored
@@ -126,14 +126,15 @@ module VX_bank_core_req_arb #(
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end else begin
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pop_mask[sel_idx] <= 1;
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end
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end
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if ((0 == q_valids_cnt_r) || pop) begin
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sel_tid <= sel_idx;
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sel_byteen <= q_byteen[sel_idx];
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sel_addr <= q_addr[sel_idx];
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sel_writedata <= q_writedata[sel_idx];
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end
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end
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if ((0 == q_valids_cnt_r) || pop) begin
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sel_tid <= sel_idx;
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sel_byteen <= q_byteen[sel_idx];
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sel_addr <= q_addr[sel_idx];
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sel_writedata <= q_writedata[sel_idx];
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end
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end
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if (CORE_TAG_ID_BITS != 0) begin
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10
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
10
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
@@ -123,8 +123,7 @@ module VX_cache_miss_resrv #(
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head_ptr <= 0;
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tail_ptr <= 0;
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size <= 0;
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end else begin
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end else begin
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if (update_ready_st0) begin
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ready_table <= ready_table | valid_address_match;
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end
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@@ -140,7 +139,6 @@ module VX_cache_miss_resrv #(
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end else begin
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valid_table[tail_ptr] <= 1;
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ready_table[tail_ptr] <= enqueue_ready_st3;
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addr_table[tail_ptr] <= enqueue_addr_st3;
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tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
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size <= size + $bits(size)'(1);
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end
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@@ -159,6 +157,12 @@ module VX_cache_miss_resrv #(
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end
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end
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always @(posedge clk) begin
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if (enqueue_st3 && !enqueue_msrq_st3) begin
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addr_table[tail_ptr] <= enqueue_addr_st3;
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end
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end
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VX_dp_ram #(
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.DATAW(`MRVQ_METADATA_WIDTH),
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.SIZE(MRVQ_SIZE),
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