wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

reset networks optimization

Browse Source
This commit is contained in:
Blaise Tine
2020-11-16 01:12:02 -08:00
parent 1bc4b8e7a8
commit a1fcdd467a
14 changed files with 259 additions and 219 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
hw/rtl/VX_gpr_bypass.v
View File

@@ -40,7 +40,6 @@ module VX_gpr_bypass #(
delayed_push <= push;
assert(!use_buffer2 || use_buffer);
if (pop) begin
buffer <= buffer2;
use_buffer <= use_buffer2;
use_buffer2 <= 0;
end
@@ -48,18 +47,29 @@ module VX_gpr_bypass #(
if (use_buffer) begin
assert(!use_buffer2); // full!
use_buffer <= 1;
if (pop) begin
buffer <= data_in;
end else begin
buffer2 <= data_in;
if (!pop) begin
use_buffer2 <= 1;
end
end else if (!pop) begin
buffer <= data_in;
use_buffer <= 1;
end
end
end
if (pop) begin
buffer <= buffer2;
end
if (delayed_push) begin
if (use_buffer) begin
if (pop) begin
buffer <= data_in;
end else begin
buffer2 <= data_in;
end
end else if (!pop) begin
buffer <= data_in;
end
end
end
assign data_out = use_buffer ? buffer : data_in;

32
hw/rtl/VX_gpr_stage.v
View File

@@ -38,15 +38,16 @@ module VX_gpr_stage #(
always @(posedge clk) begin
if (reset) begin
rsp_valid <= 0;
rsp_valid <= 0;
end else begin
rsp_valid <= gpr_req_if.valid;
rsp_wid <= gpr_req_if.wid;
rsp_pc <= gpr_req_if.PC;
rs1_is_zero <= (0 == gpr_req_if.rs1);
rs2_is_zero <= (0 == gpr_req_if.rs2);
rsp_valid <= gpr_req_if.valid;
end
end
rsp_wid <= gpr_req_if.wid;
rsp_pc <= gpr_req_if.PC;
rs1_is_zero <= (0 == gpr_req_if.rs1);
rs2_is_zero <= (0 == gpr_req_if.rs2);
end
`ifdef EXT_F_ENABLE
@@ -62,16 +63,19 @@ module VX_gpr_stage #(
end else begin
if (rs3_delay) begin
read_rs3 <= 1;
save_rs3 <= 1;
end else if (read_fire) begin
read_rs3 <= 0;
end
if (save_rs3) begin
rs3_data <= rs1_data;
save_rs3 <= 0;
end
end
assert(!read_rs3 || rsp_wid == gpr_req_if.wid);
end
end
if (rs3_delay) begin
save_rs3 <= 1;
end
if (save_rs3) begin
rs3_data <= rs1_data;
save_rs3 <= 0;
end
end
assign raddr1 = {gpr_req_if.wid, (rs3_delay ? gpr_req_if.rs3 : gpr_req_if.rs1)};

27
hw/rtl/VX_ibuffer.v
View File

@@ -60,23 +60,20 @@ module VX_ibuffer #(
if (reset) begin
size_r[i] <= 0;
end else begin
if (writing) begin
if (is_slot0) begin
q_data_out[i] <= q_data_in;
end
if (!reading) begin
size_r[i] <= size_r[i] + SIZEW'(1);
end
if (writing && !reading) begin
size_r[i] <= size_r[i] + SIZEW'(1);
end
if (reading) begin
if (size_r[i] != 1) begin
q_data_out[i] <= q_data_prev[i];
end
if (!writing) begin
size_r[i] <= size_r[i] - SIZEW'(1);
end
if (reading && !writing) begin
size_r[i] <= size_r[i] - SIZEW'(1);
end
end
end
if (writing && is_slot0) begin
q_data_out[i] <= q_data_in;
end
if (reading && (size_r[i] != 1)) begin
q_data_out[i] <= q_data_prev[i];
end
end
assign q_full[i] = (size_r[i] == SIZE);

13
hw/rtl/cache/VX_bank_core_req_arb.v vendored
View File

@@ -126,14 +126,15 @@ module VX_bank_core_req_arb #(
end else begin
pop_mask[sel_idx] <= 1;
end
end
if ((0 == q_valids_cnt_r) || pop) begin
sel_tid <= sel_idx;
sel_byteen <= q_byteen[sel_idx];
sel_addr <= q_addr[sel_idx];
sel_writedata <= q_writedata[sel_idx];
end
end
if ((0 == q_valids_cnt_r) || pop) begin
sel_tid <= sel_idx;
sel_byteen <= q_byteen[sel_idx];
sel_addr <= q_addr[sel_idx];
sel_writedata <= q_writedata[sel_idx];
end
end
if (CORE_TAG_ID_BITS != 0) begin

10
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -123,8 +123,7 @@ module VX_cache_miss_resrv #(
head_ptr <= 0;
tail_ptr <= 0;
size <= 0;
end else begin
end else begin
if (update_ready_st0) begin
ready_table <= ready_table | valid_address_match;
end
@@ -140,7 +139,6 @@ module VX_cache_miss_resrv #(
end else begin
valid_table[tail_ptr] <= 1;
ready_table[tail_ptr] <= enqueue_ready_st3;
addr_table[tail_ptr] <= enqueue_addr_st3;
tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
size <= size + $bits(size)'(1);
end
@@ -159,6 +157,12 @@ module VX_cache_miss_resrv #(
end
end
always @(posedge clk) begin
if (enqueue_st3 && !enqueue_msrq_st3) begin
addr_table[tail_ptr] <= enqueue_addr_st3;
end
end
VX_dp_ram #(
.DATAW(`MRVQ_METADATA_WIDTH),
.SIZE(MRVQ_SIZE),

5
hw/rtl/libs/VX_bypass_buffer.v
View File

@@ -32,10 +32,13 @@ module VX_bypass_buffer #(
end
if (valid_in && ~ready_out) begin
assert(!buffer_valid);
buffer <= data_in;
buffer_valid <= 1;
end
end
if (valid_in && ~ready_out) begin
buffer <= data_in;
end
end
assign ready_in = ready_out || !buffer_valid;

9
hw/rtl/libs/VX_cam_buffer.v
View File

@@ -52,10 +52,6 @@ module VX_cam_buffer #(
full_r <= 1'b0;
write_addr_r <= ADDRW'(1'b0);
end else begin
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $display("%t: inused slot at port %d", $time, write_addr);
entries[write_addr] <= write_data;
end
for (integer i = 0; i < CPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[release_addr[i]]) else $display("%t: freed slot at port %d", $time, release_addr[i]);
@@ -65,6 +61,11 @@ module VX_cam_buffer #(
write_addr_r <= free_index;
full_r <= ~free_valid;
end
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $display("%t: inused slot at port %d", $time, write_addr);
entries[write_addr] <= write_data;
end
end
for (genvar i = 0; i < RPORTS; i++) begin

5
hw/rtl/libs/VX_index_queue.v
View File

@@ -42,7 +42,6 @@ module VX_index_queue #(
valid <= 0;
end else begin
if (enqueue) begin
entries[wr_a] <= write_data;
valid[wr_a] <= 1;
wr_ptr <= wr_ptr + 1;
end
@@ -53,6 +52,10 @@ module VX_index_queue #(
valid[read_addr] <= 0;
end
end
if (enqueue) begin
entries[wr_a] <= write_data;
end
end
assign write_addr = wr_a;

15
hw/rtl/libs/VX_scope.v
View File

@@ -77,6 +77,7 @@ module VX_scope #(
read_delta <= 0;
data_valid <= 0;
timestamp <= 0;
start_time <= 0;
end else begin
timestamp <= timestamp + 1;
@@ -177,6 +178,20 @@ module VX_scope #(
end
end
end
if (recording) begin
if (UPDW_ENABLE) begin
if (delta_flush
|| changed
|| (trigger_id != prev_trigger_id)) begin
delta_store[waddr] <= delta;
data_store[waddr] <= data_in;
end
end else begin
delta_store[waddr] <= 0;
data_store[waddr] <= data_in;
end
end
end
always @(*) begin

38
hw/rtl/libs/VX_serial_div.v
View File

@@ -58,32 +58,32 @@ module VX_serial_div #(
if (reset) begin
cntr <= 0;
is_busy <= 0;
end
else begin
end else begin
if (push) begin
for (integer i = 0; i < LANES; ++i) begin
working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
denom_r[i] <= denom_qual[i];
inv_quot[i] <= (denom[i] != 0) && signed_mode && (numer[i][31] ^ denom[i][31]);
inv_rem[i] <= signed_mode && numer[i][31];
end
tag_r <= tag_in;
cntr <= WIDTHN;
cntr <= WIDTHN;
is_busy <= 1;
end
else begin
if (!done) begin
for (integer i = 0; i < LANES; ++i) begin
working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
end
cntr <= cntr - CNTRW'(1);
end
end else if (!done) begin
cntr <= cntr - CNTRW'(1);
end
if (pop) begin
is_busy <= 0;
end
end
if (push) begin
for (integer i = 0; i < LANES; ++i) begin
working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
denom_r[i] <= denom_qual[i];
inv_quot[i] <= (denom[i] != 0) && signed_mode && (numer[i][31] ^ denom[i][31]);
inv_rem[i] <= signed_mode && numer[i][31];
end
tag_r <= tag_in;
end else if (!done) begin
for (integer i = 0; i < LANES; ++i) begin
working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
end
end
end
for (genvar i = 0; i < LANES; ++i) begin

18
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -27,18 +27,22 @@ module VX_skid_buffer #(
if (ready_out) begin
use_buffer <= 0;
end
if (push) begin
buffer <= data_in;
if (valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
data_out_r <= use_buffer ? buffer : data_in;
end
end
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
end
assign ready_in = !use_buffer;