rtl cache refactory

2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
--- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v
+++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v
@@ -4,12 +4,14 @@
 `include "../cache/VX_cache_config.vh"

 interface VX_cache_dram_rsp_if #(
-    parameter BANK_LINE_WORDS = 2
+    parameter DRAM_LINE_WIDTH = 1,
+    parameter DRAM_TAG_WIDTH  = 1
 ) ();
-    // DRAM Response
-    wire                             dram_rsp_valid;
-    wire [31:0]                      dram_rsp_addr;
-    wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data;
+
+    wire                        dram_rsp_valid;
+    wire [DRAM_LINE_WIDTH-1:0]  dram_rsp_data;
+    wire [DRAM_TAG_WIDTH-1:0]   dram_rsp_tag;  
+    wire                        dram_rsp_ready;      

 endinterface