rtl cache refactory

hw/rtl/interfaces/VX_cache_dram_req_if.v

@@ -4,17 +4,17 @@
 `include "../cache/VX_cache_config.vh"
 
 interface VX_cache_dram_req_if #(
-    parameter BANK_LINE_WORDS = 2
+    parameter DRAM_LINE_WIDTH = 1,
+    parameter DRAM_ADDR_WIDTH = 1,
+    parameter DRAM_TAG_WIDTH  = 1
 ) ();
 
-    // DRAM Request
-    wire                              dram_req_write;
-    wire                              dram_req_read;
-    wire [31:0]                       dram_req_addr;
-    wire [BANK_LINE_WORDS-1:0][31:0]  dram_req_data;    
-    wire                              dram_req_ready;
-
-    wire                              dram_rsp_ready;    
+    wire                        dram_req_read;
+    wire                        dram_req_write;    
+    wire [DRAM_ADDR_WIDTH-1:0]  dram_req_addr;
+    wire [DRAM_LINE_WIDTH-1:0]  dram_req_data;  
+    wire [DRAM_TAG_WIDTH-1:0]   dram_req_tag;    
+    wire                        dram_req_ready;
 
 endinterface