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rtl cache refactory

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This commit is contained in:
Blaise Tine
2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
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24
hw/rtl/interfaces/VX_cache_core_req_if.v
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@@ -4,22 +4,18 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_core_req_if #(
parameter NUM_REQUESTS = 32
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
// Core request
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][2:0] core_req_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_data;
wire core_req_ready;
// Core request Meta data
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_read;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
wire core_req_ready;
endinterface

20
hw/rtl/interfaces/VX_cache_core_rsp_if.v
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@@ -4,21 +4,15 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_core_rsp_if #(
parameter NUM_REQUESTS = 32
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
// Core response
wire [NUM_REQUESTS-1:0] core_rsp_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_rsp_read;
wire [1:0] core_rsp_write;
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_data;
wire core_rsp_ready;
// Core response meta data
wire [`NW_BITS-1:0] core_rsp_warp_num;
wire [NUM_REQUESTS-1:0] core_rsp_valid;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag;
wire core_rsp_ready;
endinterface

18
hw/rtl/interfaces/VX_cache_dram_req_if.v
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@@ -4,17 +4,17 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_dram_req_if #(
parameter BANK_LINE_WORDS = 2
parameter DRAM_LINE_WIDTH = 1,
parameter DRAM_ADDR_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
) ();
// DRAM Request
wire dram_req_write;
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire dram_req_ready;
wire dram_rsp_ready;
wire dram_req_read;
wire dram_req_write;
wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr;
wire [DRAM_LINE_WIDTH-1:0] dram_req_data;
wire [DRAM_TAG_WIDTH-1:0] dram_req_tag;
wire dram_req_ready;
endinterface

12
hw/rtl/interfaces/VX_cache_dram_rsp_if.v
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@@ -4,12 +4,14 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_dram_rsp_if #(
parameter BANK_LINE_WORDS = 2
parameter DRAM_LINE_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
) ();
// DRAM Response
wire dram_rsp_valid;
wire [31:0] dram_rsp_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data;
wire dram_rsp_valid;
wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data;
wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag;
wire dram_rsp_ready;
endinterface

10
hw/rtl/interfaces/VX_cache_snp_req_if.v
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@@ -3,11 +3,13 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_snp_req_if ();
interface VX_cache_snp_req_if #(
parameter DRAM_ADDR_WIDTH = 1
) ();
wire snp_req_valid;
wire [31:0] snp_req_addr;
wire snp_req_ready;
wire snp_req_valid;
wire [DRAM_ADDR_WIDTH-1:0] snp_req_addr;
wire snp_req_ready;
endinterface

17
hw/rtl/interfaces/VX_csr_wb_if.v
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@@ -1,17 +0,0 @@
`ifndef VX_CSR_WB_IF
`define VX_CSR_WB_IF
`include "VX_define.vh"
interface VX_csr_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0][31:0] csr_result;
endinterface
`endif

4
hw/rtl/interfaces/VX_frE_to_bckE_req_if.v
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@@ -16,8 +16,8 @@ interface VX_frE_to_bckE_req_if ();
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [`WORD_SEL_BITS-1:0] mem_read;
wire [`WORD_SEL_BITS-1:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire [31:0] curr_PC;

2
hw/rtl/interfaces/VX_gpgpu_inst_req_if.v → hw/rtl/interfaces/VX_gpu_inst_req_if.v
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@@ -3,7 +3,7 @@
`include "VX_define.vh"
interface VX_gpgpu_inst_req_if();
interface VX_gpu_inst_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;

18
hw/rtl/interfaces/VX_inst_exec_wb_if.v
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@@ -1,18 +0,0 @@
`ifndef VX_INST_EXEC_WB_IF
`define VX_INST_EXEC_WB_IF
`include "VX_define.vh"
interface VX_inst_exec_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [31:0] exec_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface
`endif

18
hw/rtl/interfaces/VX_inst_mem_wb_if.v
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@@ -1,18 +0,0 @@
`ifndef VX_INST_MEM_WB_IF
`define VX_INST_MEM_WB_IF
`include "VX_define.vh"
interface VX_inst_mem_wb_if ();
wire [`NUM_THREADS-1:0][31:0] loaded_data;
wire [31:0] mem_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface
`endif

2
hw/rtl/interfaces/VX_inst_meta_if.v
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@@ -8,7 +8,7 @@ interface VX_inst_meta_if ();
wire [31:0] instruction;
wire [31:0] inst_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] valid;
wire [`NUM_THREADS-1:0] valid;
endinterface

20
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -6,16 +6,16 @@
interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [`WORD_SEL_BITS-1:0] mem_read;
wire [`WORD_SEL_BITS-1:0] mem_write;
wire [4:0] rd; // dest register
wire [1:0] wb; //
endinterface

10
hw/rtl/interfaces/VX_wb_if.v
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@@ -5,12 +5,12 @@
interface VX_wb_if ();
wire [`NUM_THREADS-1:0][31:0] write_data;
wire [31:0] wb_pc;
wire [`NUM_THREADS-1:0] valid;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
wire [1:0] wb;
wire [31:0] pc;
endinterface