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rtl cache refactory

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This commit is contained in:
Blaise Tine
2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
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40
hw/rtl/cache/VX_prefetcher.v vendored
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@@ -1,29 +1,29 @@
`include "VX_cache_config.vh"
module VX_prefetcher #(
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4
parameter WORD_SIZE = 4
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
input wire dram_req,
input wire[31:0] dram_req_addr,
input wire dram_req,
input wire[`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
input wire pref_pop,
output wire pref_valid,
output wire[31:0] pref_addr
input wire pref_pop,
output wire pref_valid,
output wire[`DRAM_ADDR_WIDTH-1:0] pref_addr
);
reg[`LOG2UP(PRFQ_STRIDE):0] use_valid;
reg[31:0] use_addr;
reg[`LOG2UP(PRFQ_STRIDE):0] use_valid;
reg[`DRAM_ADDR_WIDTH-1:0] use_addr;
wire current_valid;
wire[31:0] current_addr;
wire current_valid;
wire[`DRAM_ADDR_WIDTH-1:0] current_addr;
wire current_full;
wire current_empty;
@@ -33,14 +33,14 @@ module VX_prefetcher #(
wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid;
VX_generic_queue #(
.DATAW(32),
.DATAW(`DRAM_ADDR_WIDTH),
.SIZE(PRFQ_SIZE)
) pfq_queue (
.clk (clk),
.reset (reset),
.push (dram_req && !current_full && !pref_pop),
.data_in (dram_req_addr & `BASE_ADDR_MASK),
.data_in (dram_req_addr),
.pop (update_use),
.data_out(current_addr),
@@ -49,7 +49,7 @@ module VX_prefetcher #(
.full (current_full)
);
assign pref_valid = use_valid != 0;
assign pref_valid = 0; // TODO use_valid != 0;
assign pref_addr = use_addr;
always @(posedge clk) begin
@@ -59,10 +59,10 @@ module VX_prefetcher #(
end else begin
if (update_use) begin
use_valid <= PRFQ_STRIDE;
use_addr <= current_addr + BANK_LINE_SIZE_BYTES;
use_addr <= current_addr + BANK_LINE_SIZE;
end else if (pref_valid && pref_pop) begin
use_valid <= use_valid - 1;
use_addr <= use_addr + BANK_LINE_SIZE_BYTES;
use_addr <= use_addr + BANK_LINE_SIZE;
end
end
end