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rtl cache refactory

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This commit is contained in:
Blaise Tine
2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
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81
hw/rtl/cache/VX_fill_invalidator.v vendored
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@@ -2,13 +2,13 @@
module VX_fill_invalidator #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@@ -35,20 +35,17 @@ module VX_fill_invalidator #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter FILL_INVALIDAOR_SIZE = 16
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
input wire possible_fill,
input wire success_fill,
input wire possible_fill,
input wire success_fill,
input wire[31:0] fill_addr,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr,
output reg invalidate_fill
output reg invalidate_fill
);
if (FILL_INVALIDAOR_SIZE == 0) begin
@@ -57,15 +54,16 @@ module VX_fill_invalidator #(
end else begin
reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;
reg [FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address;
reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;
reg [FILL_INVALIDAOR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] fills_address;
reg [FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer fi;
always @(*) begin
for (fi = 0; fi < FILL_INVALIDAOR_SIZE; fi+=1) begin
matched_fill[fi] = fills_active[fi] && (fills_address[fi][31:`LINE_SELECT_ADDR_START] == fill_addr[31:`LINE_SELECT_ADDR_START]);
matched_fill[fi] = fills_active[fi] && (fills_address[fi] == fill_addr);
end
end
@@ -89,7 +87,6 @@ module VX_fill_invalidator #(
fills_active <= 0;
fills_address <= 0;
end else begin
if (possible_fill && !matched && enqueue_found) begin
fills_active [enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
@@ -99,56 +96,6 @@ module VX_fill_invalidator #(
end
end
// reg success_found;
// reg[(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] success_index;
// integer curr_fill;
// always @(*) begin
// invalidate_fill = 0;
// success_found = 0;
// success_index = 0;
// for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
// if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
// if (possible_fill && fills_active[curr_fill]) begin
// invalidate_fill = 1;
// end
// if (success_fill) begin
// success_found = 1;
// success_index = curr_fill;
// end
// end
// end
// end
// wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
// wire enqueue_found;
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) sel_bank(
// .valids(~fills_active),
// .index (enqueue_index),
// .found (enqueue_found)
// );
// always @(posedge clk) begin
// if (reset) begin
// fills_active <= 0;
// fills_address <= 0;
// end else begin
// if (possible_fill && !invalidate_fill) begin
// fills_active[enqueue_index] <= 1;
// fills_address[enqueue_index] <= fill_addr;
// end
// if (success_found) begin
// fills_active[success_index] <= 0;
// end
// end
// end
end
endmodule