wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rtl cache refactory

Browse Source
This commit is contained in:
Blaise Tine
2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
driver/rtlsim/Makefile
View File

@@ -1,45 +1,43 @@
CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
# CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
USE_MULTICORE=1
CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime
MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2
#DEBUG = 1
CFLAGS += -fPIC
CFLAGS += -DUSE_RTLSIM
CFLAGS += -DUSE_RTLSIM $(MULTICORE)
LDFLAGS += -shared -pthread
ifdef USE_MULTICORE
CFLAGS += -DUSE_MULTICORE
RTL_TOP = Vortex_Socket
else
VL_FLAGS += -DSINGLE_CORE_BENCH
RTL_TOP = Vortex
endif
SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache
VL_FLAGS += -DNDEBUG --assert -Wall -Wpedantic
VL_FLAGS += --assert -Wall -Wpedantic $(MULTICORE)
# Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
#VL_FLAGS += --threads $(THREADS)
# Debugigng
#VL_FLAGS += --trace -DVL_DEBUG=1
#CFLAGS += -DVCD_OUTPUT
ifdef DEBUG
VL_FLAGS += --trace -DVL_DEBUG=1
CFLAGS += -DVCD_OUTPUT
else
CFLAGS += -DNDEBUG
VL_FLAGS += -DNDEBUG
endif
PROJECT = libvortex.so
all: $(PROJECT)
$(PROJECT): $(SRCS)
verilator --exe --cc $(RTL_TOP).v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
make -j -C obj_dir -f V$(RTL_TOP).mk
verilator --exe --cc Vortex_Socket.v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
make -j -C obj_dir -f VVortex_Socket.mk
clean:
rm -rf $(PROJECT) obj_dir