RTL code refactoring

hw/unit_tests/generic_queue/testbench.v

@@ -1,5 +1,5 @@
 `timescale 1ns/1ns
-`include "VX_generic_queue_ll.v"
+`include "VX_generic_queue.v"
 
 `define check(x, y) if ((x == y) !== 1) if ((x == y) === 0) $error("x=%h, expected=%h", x, y); else $warning("x=%h, expected=%h", x, y)
 
@@ -14,7 +14,7 @@ module testbench();
   wire full;
   wire empty;
 
-  VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut (
+  VX_generic_queue #(.DATAW(4), .SIZE(4)) dut (
                                 .clk(clk), 
                                 .reset(reset), 
                                 .in_data(in_data),