RTL code refactoring

2020-04-20 13:01:42 -04:00
parent e8a4923eb4
commit a0e15af0dc
16 changed files with 149 additions and 202 deletions
--- a/hw/syn/yosys/synthesis.ys
+++ b/hw/syn/yosys/synthesis.ys
@@ -1,5 +1,5 @@
 # load design
-read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs  ../../rtl/Vortex.v
+read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache  ../../rtl/Vortex.v

 # high-level synthesis
 proc; opt; fsm;; memory -nomap; opt