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RTL code refactoring

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Blaise Tine
2020-04-20 13:01:42 -04:00
parent e8a4923eb4
commit a0e15af0dc
16 changed files with 149 additions and 202 deletions
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2
hw/syn/quartus/top/Makefile
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@@ -57,7 +57,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache;../shared_memory"
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache"
syn.chg:
$(STAMP) syn.chg

2
hw/syn/yosys/synthesis.ys
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@@ -1,5 +1,5 @@
# load design
read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs ../../rtl/Vortex.v
read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v
# high-level synthesis
proc; opt; fsm;; memory -nomap; opt