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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 13:01:42 -04:00
parent e8a4923eb4
commit a0e15af0dc
16 changed files with 149 additions and 202 deletions
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4
hw/modelsim/Makefile
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@@ -71,10 +71,6 @@ SRC = \
../rtl/cache/VX_cache_data_per_index.v \
../rtl/pipe_regs/VX_d_e_reg.v \
../rtl/pipe_regs/VX_f_d_reg.v \
../rtl/shared_memory/VX_bank_valids.v \
../rtl/shared_memory/VX_priority_encoder_sm.v \
../rtl/shared_memory/VX_shared_memory.v \
../rtl/shared_memory/VX_shared_memory_block.v \
../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \