diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 3cea4364..fb246b05 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -264,7 +264,7 @@ // Size of cache in bytes `ifndef ICACHE_SIZE -`define ICACHE_SIZE 8192 +`define ICACHE_SIZE 16384 `endif // Core Request Queue Size @@ -296,7 +296,7 @@ // Size of cache in bytes `ifndef DCACHE_SIZE -`define DCACHE_SIZE 8192 +`define DCACHE_SIZE 16384 `endif // Number of banks @@ -360,7 +360,7 @@ // Size of cache in bytes `ifndef L2CACHE_SIZE -`define L2CACHE_SIZE 131072 +`define L2CACHE_SIZE 65536 `endif // Number of banks diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index 5cf9c50c..2589346d 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -43,7 +43,6 @@ module VX_ibuffer #( VX_fifo_queue #( .DATAW (DATAW), .SIZE (SIZE), - .BUFFERED (1), .FASTRAM (1) ) queue ( .clk (clk), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 08c9dbef..47d6b964 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -165,7 +165,7 @@ module Vortex ( VX_cache #( .CACHE_ID (`L3CACHE_ID), .CACHE_SIZE (`L3CACHE_SIZE), - .CACHE_LINE_SIZE (`L3CACHE_LINE_SIZE), + .CACHE_LINE_SIZE (`L3CACHE_LINE_SIZE), .NUM_BANKS (`L3NUM_BANKS), .WORD_SIZE (`L3WORD_SIZE), .NUM_REQS (`NUM_CLUSTERS), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 9df1c8f0..66a0ab89 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -117,7 +117,6 @@ module VX_bank #( .data_out_next ({drsq_addr_next, drsq_filldata_next, drsq_flush_next}), .empty_next (drsq_empty_next), .full (drsq_full), - `UNUSED_PIN (almost_full), `UNUSED_PIN (size) ); @@ -164,12 +163,14 @@ module VX_bank #( .data_out_next({creq_tag_next, creq_tid_next, creq_rw_next, creq_byteen_next, creq_addr_next_unqual, creq_writeword_next}), `UNUSED_PIN (empty_next), .full (creq_full), - `UNUSED_PIN (almost_full), `UNUSED_PIN (size) - ); + ); - wire mshr_pop; - wire mshr_almost_full; + wire crsq_alm_full; + wire dreq_alm_full; + wire mshr_alm_full; + + wire mshr_pop; wire mshr_pending_unqual_st0; wire mshr_valid; wire mshr_valid_next; @@ -181,14 +182,11 @@ module VX_bank #( wire mshr_rw_next; wire [WORD_SIZE-1:0] mshr_byteen_next; - wire dreq_almost_full; - wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1; wire [`UP(`WORD_SELECT_BITS)-1:0] wsel_st0, wsel_st1; wire mem_rw_st0, mem_rw_st1; wire [WORD_SIZE-1:0] byteen_st0, byteen_st1; - wire [`WORD_WIDTH-1:0] writeword_st0, writeword_st1; - wire [`CACHE_LINE_WIDTH-1:0] filldata_st0, filldata_st1; + wire [`CACHE_LINE_WIDTH-1:0] data_st0, data_st1; wire [`REQS_BITS-1:0] req_tid_st0, req_tid_st1; wire [`REQ_TAG_WIDTH-1:0] tag_st0, tag_st1; wire valid_st0, valid_st1; @@ -199,35 +197,35 @@ module VX_bank #( wire force_miss_st0, force_miss_st1; wire do_writeback_st0, do_writeback_st1; wire writeen_unqual_st0, writeen_unqual_st1; - wire mshr_push_unqual_st0, mshr_push_unqual_st1; wire dreq_push_unqual_st0, dreq_push_unqual_st1; wire writeen_st1; wire core_req_hit_st1; wire is_flush_st0; - - wire mshr_push_stall; - wire crsq_push_stall; - wire dreq_push_stall; - wire pipeline_stall; wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1); // determine which queue to pop next in piority order wire mshr_pop_unqual = mshr_valid; wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty; - wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full; + wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty; - assign mshr_pop = mshr_pop_unqual && !pipeline_stall - && !is_mshr_miss_st1; // do not schedule another mshr request when the previous one missed - assign drsq_pop = drsq_pop_unqual && !pipeline_stall; - assign creq_pop = creq_pop_unqual && !pipeline_stall; + assign mshr_pop = mshr_pop_unqual + && !crsq_alm_full // ensure core response ready + && !is_mshr_miss_st1; // do not schedule another mshr request when the previous one missed + + assign drsq_pop = drsq_pop_unqual; + + assign creq_pop = creq_pop_unqual + && !crsq_alm_full // ensure core response ready + && !dreq_alm_full // ensure dram request ready + && !mshr_alm_full; // ensure mshr enqueue ready assign valid_st0 = mshr_pop || drsq_pop || creq_pop; assign is_mshr_st0 = mshr_pop_unqual; assign is_fill_st0 = drsq_pop_unqual; VX_pipe_register #( - .DATAW (`LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + 1 + WORD_SIZE + `WORD_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + `CACHE_LINE_WIDTH + 1), + .DATAW (`LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + 1 + WORD_SIZE + `CACHE_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + 1), .RESETW (0) ) pipe_reg0 ( .clk (clk), @@ -238,13 +236,12 @@ module VX_bank #( mshr_valid_next ? mshr_wsel_next : creq_wsel_next, mshr_valid_next ? mshr_rw_next : creq_rw_next, mshr_valid_next ? mshr_byteen_next : creq_byteen_next, - mshr_valid_next ? mshr_writeword_next : creq_writeword_next, + mshr_valid_next ? {`WORDS_PER_LINE{mshr_writeword_next}} : (!drsq_empty_next ? drsq_filldata_next : {`WORDS_PER_LINE{creq_writeword_next}}), mshr_valid_next ? mshr_tid_next : creq_tid_next, mshr_valid_next ? `REQ_TAG_WIDTH'(mshr_tag_next) : `REQ_TAG_WIDTH'(creq_tag_next), - drsq_filldata_next, drsq_flush_next }), - .data_out ({addr_st0, wsel_st0, mem_rw_st0, byteen_st0, writeword_st0, req_tid_st0, tag_st0, filldata_st0, is_flush_st0}) + .data_out ({addr_st0, wsel_st0, mem_rw_st0, byteen_st0, data_st0, req_tid_st0, tag_st0, is_flush_st0}) ); `ifdef DBG_CACHE_REQ_INFO @@ -300,17 +297,15 @@ module VX_bank #( assign dreq_push_unqual_st0 = send_fill_req_st0 || do_writeback_st0; - assign mshr_push_unqual_st0 = !is_fill_st0 && !mem_rw_st0; - VX_pipe_register #( - .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + `WORD_WIDTH + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), .RESETW (1) ) pipe_reg1 ( .clk (clk), .reset (reset), - .enable (!pipeline_stall), - .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, mshr_push_unqual_st0, dreq_push_unqual_st0, do_writeback_st0, miss_st0, force_miss_st0, addr_st0, wsel_st0, writeword_st0, filldata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}), - .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, mshr_push_unqual_st1, dreq_push_unqual_st1, do_writeback_st1, miss_st1, force_miss_st1, addr_st1, wsel_st1, writeword_st1, filldata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}) + .enable (1'b1), + .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, dreq_push_unqual_st0, do_writeback_st0, miss_st0, force_miss_st0, addr_st0, wsel_st0, data_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}), + .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, dreq_push_unqual_st1, do_writeback_st1, miss_st1, force_miss_st1, addr_st1, wsel_st1, data_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}) ); assign core_req_hit_st1 = !is_fill_st1 && !miss_st1 && !force_miss_st1; @@ -319,7 +314,7 @@ module VX_bank #( wire dreq_push_st1 = dreq_push_unqual_st1 && (do_writeback_st1 || !force_miss_st1); - wire mshr_push_st1 = mshr_push_unqual_st1 && (miss_st1 || force_miss_st1); + wire mshr_push_st1 = !is_fill_st1 && !mem_rw_st1 && (miss_st1 || force_miss_st1); wire crsq_push_st1 = core_req_hit_st1 && !mem_rw_st1; @@ -333,27 +328,26 @@ module VX_bank #( .WORD_SIZE (WORD_SIZE), .WRITE_ENABLE (WRITE_ENABLE) ) data_access ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), `ifdef DBG_CACHE_REQ_INFO - .debug_pc (debug_pc_st1), - .debug_wid (debug_wid_st1), + .debug_pc (debug_pc_st1), + .debug_wid (debug_wid_st1), `endif - .addr (addr_st1), + .addr (addr_st1), // reading - .readen (valid_st1 && !mem_rw_st1 && !is_fill_st1 && ~pipeline_stall), - .readdata (readdata_st1), + .readen (valid_st1 && !mem_rw_st1 && !is_fill_st1), + .rddata (readdata_st1), - // writing - .writeen (valid_st1 && writeen_st1 && ~pipeline_stall), - .is_fill (is_fill_st1), - .wsel (wsel_st1), - .byteen (byteen_st1), - .writeword (writeword_st1), - .filldata (filldata_st1) + // writing + .writeen (valid_st1 && writeen_st1), + .is_fill (is_fill_st1), + .wsel (wsel_st1), + .byteen (byteen_st1), + .wrdata (data_st1) ); `ifdef DBG_CACHE_REQ_INFO @@ -364,20 +358,14 @@ module VX_bank #( end `endif - wire mshr_push_unqual = valid_st1 && mshr_push_st1; - assign mshr_push_stall = 0; - - wire mshr_push = mshr_push_unqual - && !crsq_push_stall - && !dreq_push_stall; - wire incoming_fill_st1 = valid_st0 && is_fill_st0 && (addr_st1 == addr_st0); - wire mshr_dequeue_st1 = valid_st1 && is_mshr_st1 && !mshr_push_unqual && !pipeline_stall; + wire mshr_push = valid_st1 && mshr_push_st1; + wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1; // push a missed request as 'ready' if it was a forced miss that actually had a hit // or the fill request for this block is comming - wire mshr_init_ready_state_st1 = !miss_st1 || incoming_fill_st1; + wire mshr_init_ready_state = !miss_st1 || incoming_fill_st1; VX_miss_resrv #( .BANK_ID (BANK_ID), @@ -404,10 +392,10 @@ module VX_bank #( // enqueue .enqueue (mshr_push), .enqueue_addr (addr_st1), - .enqueue_data ({writeword_st1, req_tid_st1, tag_st1, mem_rw_st1, byteen_st1, wsel_st1}), + .enqueue_data ({data_st1[`WORD_WIDTH-1:0], req_tid_st1, tag_st1, mem_rw_st1, byteen_st1, wsel_st1}), .enqueue_is_mshr (is_mshr_st1), - .enqueue_as_ready (mshr_init_ready_state_st1), - .enqueue_almfull (mshr_almost_full), + .enqueue_as_ready (mshr_init_ready_state), + .enqueue_almfull (mshr_alm_full), // lookup .lookup_ready (drsq_pop && !is_flush_st0), @@ -424,22 +412,15 @@ module VX_bank #( .schedule_data_next ({mshr_writeword_next, mshr_tid_next, mshr_tag_next, mshr_rw_next, mshr_byteen_next, mshr_wsel_next}), // dequeue - .dequeue (mshr_dequeue_st1) + .dequeue (mshr_dequeue) ); // Enqueue core response - wire crsq_empty, crsq_full; + wire crsq_empty; - wire crsq_push_unqual = valid_st1 && crsq_push_st1; - assign crsq_push_stall = crsq_push_unqual && crsq_full; - - wire crsq_push = crsq_push_unqual - && !crsq_full - && !mshr_push_stall - && !dreq_push_stall; - - wire crsq_pop = core_rsp_valid && core_rsp_ready; + wire crsq_push = valid_st1 && crsq_push_st1; + wire crsq_pop = core_rsp_valid && core_rsp_ready; wire [`REQS_BITS-1:0] crsq_tid_st1 = req_tid_st1; wire [CORE_TAG_WIDTH-1:0] crsq_tag_st1 = CORE_TAG_WIDTH'(tag_st1); @@ -459,7 +440,8 @@ module VX_bank #( VX_fifo_queue #( .DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH), .SIZE (CRSQ_SIZE), - .BUFFERED (NUM_BANKS == 1), + .ALM_FULL (CRSQ_SIZE-1), + .BUFFERED (1), .FASTRAM (1) ) core_rsp_queue ( .clk (clk), @@ -469,9 +451,9 @@ module VX_bank #( .data_in ({crsq_tid_st1, crsq_tag_st1, crsq_data_st1}), .data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}), .empty (crsq_empty), - .full (crsq_full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (alm_full), + .alm_full(crsq_alm_full), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), `UNUSED_PIN (size) ); @@ -480,14 +462,9 @@ module VX_bank #( // Enqueue DRAM request wire dreq_empty; - - wire dreq_push_unqual = valid_st1 && dreq_push_st1; - assign dreq_push_stall = 0; - - wire dreq_push = dreq_push_unqual - && (do_writeback_st1 || !incoming_fill_st1) - && !mshr_push_stall - && !crsq_push_stall; + + wire dreq_push = valid_st1 && dreq_push_st1 + && (do_writeback_st1 || !incoming_fill_st1); wire dreq_pop = dram_req_valid && dram_req_ready; @@ -501,12 +478,11 @@ module VX_bank #( if (`WORD_SELECT_BITS != 0) begin for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin assign dreq_byteen_unqual[i * WORD_SIZE +: WORD_SIZE] = (wsel_st1 == `WORD_SELECT_BITS'(i)) ? byteen_st1 : {WORD_SIZE{1'b0}}; - assign dreq_data[i * `WORD_WIDTH +: `WORD_WIDTH] = writeword_st1; end end else begin assign dreq_byteen_unqual = byteen_st1; - assign dreq_data = writeword_st1; end + assign dreq_data = {`WORDS_PER_LINE{data_st1[`WORD_WIDTH-1:0]}}; assign dreq_byteen = writeback ? dreq_byteen_unqual : {CACHE_LINE_SIZE{1'b1}}; @@ -524,16 +500,13 @@ module VX_bank #( .data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}), .data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}), .empty (dreq_empty), - .alm_full(dreq_almost_full), + .alm_full(dreq_alm_full), `UNUSED_PIN (full), `UNUSED_PIN (alm_empty), `UNUSED_PIN (size) ); assign dram_req_valid = !dreq_empty; - - // bank pipeline stall - assign pipeline_stall = crsq_push_stall; `SCOPE_ASSIGN (valid_st0, valid_st0); `SCOPE_ASSIGN (valid_st1, valid_st1); @@ -542,15 +515,17 @@ module VX_bank #( `SCOPE_ASSIGN (miss_st0, miss_st0); `SCOPE_ASSIGN (force_miss_st0, force_miss_st0); `SCOPE_ASSIGN (mshr_push, mshr_push); - `SCOPE_ASSIGN (pipeline_stall, pipeline_stall); + `SCOPE_ASSIGN (crsq_alm_full, crsq_alm_full); + `SCOPE_ASSIGN (dreq_alm_full, dreq_alm_full); + `SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full); `SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID)); `SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); `ifdef PERF_ENABLE - assign perf_read_misses = valid_st1 && !pipeline_stall && !is_fill_st1 && !is_mshr_st1 && miss_st1 && !mem_rw_st1; - assign perf_write_misses = valid_st1 && !pipeline_stall && !is_fill_st1 && !is_mshr_st1 && miss_st1 && mem_rw_st1; - assign perf_pipe_stalls = pipeline_stall || mshr_almost_full || dreq_almost_full; - assign perf_mshr_stalls = mshr_almost_full; + assign perf_read_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && !mem_rw_st1; + assign perf_write_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && mem_rw_st1; + assign perf_pipe_stalls = crsq_alm_full || dreq_alm_full || mshr_alm_full; + assign perf_mshr_stalls = mshr_alm_full; `endif `ifdef DBG_PRINT_CACHE_BANK @@ -559,8 +534,8 @@ module VX_bank #( $display("%t: miss with incoming fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); assert(!is_mshr_st1); end - if (crsq_push_stall || mshr_almost_full || dreq_almost_full) begin - $display("%t: cache%0d:%0d pipeline-stall: mshr=%b, cwbq=%b, dwbq=%b", $time, CACHE_ID, BANK_ID, mshr_almost_full, crsq_push_stall, dreq_almost_full); + if (crsq_alm_full || dreq_alm_full || mshr_alm_full) begin + $display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_alm_full, dreq_alm_full, mshr_alm_full); end if (drsq_pop) begin if (is_flush_st0) diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 3a3557a6..fa4cb7de 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -4,7 +4,7 @@ module VX_cache #( parameter CACHE_ID = 0, // Size of cache in bytes - parameter CACHE_SIZE = 1048576, + parameter CACHE_SIZE = 16384, // Size of line inside a bank in bytes parameter CACHE_LINE_SIZE = 64, // Number of banks diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 0b59a4c5..9c6e19b8 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -34,20 +34,18 @@ module VX_data_access #( // reading input wire readen, - output wire [`CACHE_LINE_WIDTH-1:0] readdata, + output wire [`CACHE_LINE_WIDTH-1:0] rddata, // writing input wire writeen, - input wire [`UP(`WORD_SELECT_BITS)-1:0] wsel, - input wire [WORD_SIZE-1:0] byteen, input wire is_fill, - input wire [`WORD_WIDTH-1:0] writeword, - input wire [`CACHE_LINE_WIDTH-1:0] filldata + input wire [`UP(`WORD_SELECT_BITS)-1:0] wsel, + input wire [WORD_SIZE-1:0] byteen, + input wire [`CACHE_LINE_WIDTH-1:0] wrdata ); `UNUSED_VAR (reset) - wire [CACHE_LINE_SIZE-1:0] byte_enable; - wire [`CACHE_LINE_WIDTH-1:0] write_data; + wire [CACHE_LINE_SIZE-1:0] byte_enable; wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0]; @@ -62,8 +60,8 @@ module VX_data_access #( .wren(writeen), .byteen(byte_enable), .rden(1'b1), - .din(write_data), - .dout(readdata) + .din(wrdata), + .dout(rddata) ); wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] byteen_qual; @@ -78,7 +76,6 @@ module VX_data_access #( end assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen_qual; - assign write_data = is_fill ? filldata : {`WORDS_PER_LINE{writeword}}; `UNUSED_VAR (readen) diff --git a/hw/rtl/cache/VX_fifo_queue_xt.v b/hw/rtl/cache/VX_fifo_queue_xt.v index 2c5793f3..02ebe786 100644 --- a/hw/rtl/cache/VX_fifo_queue_xt.v +++ b/hw/rtl/cache/VX_fifo_queue_xt.v @@ -3,7 +3,6 @@ module VX_fifo_queue_xt #( parameter DATAW = 1, parameter SIZE = 2, - parameter ALM_FULL = (SIZE - 1), parameter ADDRW = $clog2(SIZE), parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0 @@ -18,22 +17,20 @@ module VX_fifo_queue_xt #( output wire [DATAW-1:0] data_out_next, output wire empty_next, output wire full, - output wire almost_full, output wire [SIZEW-1:0] size ); wire [DATAW-1:0] dout; reg [DATAW-1:0] dout_r, dout_n_r; reg [ADDRW-1:0] wr_ptr_r; reg [ADDRW-1:0] rd_ptr_r, rd_ptr_n_r; - reg full_r, almost_full_r; + reg full_r; reg empty_r, empty_n_r; reg [ADDRW-1:0] used_r; always @(posedge clk) begin if (reset) begin - full_r <= 0; - almost_full_r <= 0; - used_r <= 0; + full_r <= 0; + used_r <= 0; end else begin assert(!push || !full); assert(!pop || !empty_r); @@ -41,12 +38,8 @@ module VX_fifo_queue_xt #( if (!pop) begin if (used_r == ADDRW'(SIZE-1)) full_r <= 1; - if (used_r == ADDRW'(ALM_FULL-1)) - almost_full_r <= 1; end end else if (pop) begin - if (used_r == ADDRW'(ALM_FULL)) - almost_full_r <= 0; full_r <= 0; end @@ -75,11 +68,11 @@ module VX_fifo_queue_xt #( end VX_dp_ram #( - .DATAW(DATAW), - .SIZE(SIZE), - .BUFFERED(0), - .RWCHECK(1), - .FASTRAM(FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .BUFFERED (0), + .RWCHECK (1), + .FASTRAM (FASTRAM) ) dp_ram ( .clk(clk), .waddr(wr_ptr_r), @@ -127,7 +120,6 @@ module VX_fifo_queue_xt #( assign empty = empty_r; assign empty_next = empty_n_r; assign full = full_r; - assign almost_full = almost_full_r; assign size = {full_r, used_r}; endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index be5f0c0d..78f3ee89 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -186,9 +186,7 @@ module VX_miss_resrv #( if (reset) begin schedule_valid_n_r = 0; end else begin - if (restore) begin - schedule_valid_n_r = enqueue_as_ready; - end else if (lookup_ready) begin + if (lookup_ready) begin schedule_valid_n_r = schedule_valid_r || (schedule_addr_r == lookup_addr); end else if (schedule) begin schedule_valid_n_r = ready_table[schedule_n_ptr]; diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index d55d7488..a99239a6 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -166,18 +166,18 @@ module VX_shared_mem #( for (genvar i = 0; i < NUM_BANKS; i++) begin VX_sp_ram #( - .DATAW(`WORD_WIDTH), - .SIZE(`LINES_PER_BANK), - .BYTEENW(WORD_SIZE), - .RWCHECK(1) + .DATAW (`WORD_WIDTH), + .SIZE (`LINES_PER_BANK), + .BYTEENW (WORD_SIZE), + .RWCHECK (1) ) data ( - .clk(clk), - .addr(per_bank_core_req_addr[i]), - .wren(per_bank_core_req_valid[i] && per_bank_core_req_rw[i] && ~crsq_full), - .byteen(per_bank_core_req_byteen[i]), - .rden(1'b1), - .din(per_bank_core_req_data[i]), - .dout(per_bank_core_rsp_data[i]) + .clk (clk), + .addr (per_bank_core_req_addr[i]), + .wren (per_bank_core_req_valid[i] && per_bank_core_req_rw[i] && ~crsq_full), + .byteen (per_bank_core_req_byteen[i]), + .rden (1'b1), + .din (per_bank_core_req_data[i]), + .dout (per_bank_core_rsp_data[i]) ); end @@ -220,14 +220,14 @@ module VX_shared_mem #( .BUFFERED (1), .FASTRAM (1) ) core_rsp_queue ( - .clk (clk), - .reset (reset), - .push (crsq_push), - .pop (crsq_pop), - .data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}), - .data_out({core_rsp_valid_tmask, core_rsp_data, core_rsp_tag}), - .empty (crsq_empty), - .full (crsq_full), + .clk (clk), + .reset (reset), + .push (crsq_push), + .pop (crsq_pop), + .data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}), + .data_out ({core_rsp_valid_tmask, core_rsp_data, core_rsp_tag}), + .empty (crsq_empty), + .full (crsq_full), `UNUSED_PIN (alm_empty), `UNUSED_PIN (alm_full), `UNUSED_PIN (size) diff --git a/hw/rtl/libs/VX_fifo_queue.v b/hw/rtl/libs/VX_fifo_queue.v index 1dd55841..4972d568 100644 --- a/hw/rtl/libs/VX_fifo_queue.v +++ b/hw/rtl/libs/VX_fifo_queue.v @@ -1,14 +1,14 @@ `include "VX_platform.vh" module VX_fifo_queue #( - parameter DATAW = 1, - parameter SIZE = 2, - parameter ALM_FULL = (SIZE - 1), - parameter ALM_EMPTY= 1, - parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), - parameter BUFFERED = 0, - parameter FASTRAM = 1 + parameter DATAW = 1, + parameter SIZE = 2, + parameter ALM_FULL = (SIZE - 1), + parameter ALM_EMPTY = 1, + parameter ADDRW = $clog2(SIZE), + parameter SIZEW = $clog2(SIZE+1), + parameter BUFFERED = 0, + parameter FASTRAM = 1 ) ( input wire clk, input wire reset, @@ -111,11 +111,11 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW(DATAW), - .SIZE(SIZE), - .BUFFERED(0), - .RWCHECK(1), - .FASTRAM(FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .BUFFERED (0), + .RWCHECK (1), + .FASTRAM (FASTRAM) ) dp_ram ( .clk(clk), .waddr(wr_ptr_r), @@ -156,11 +156,11 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW(DATAW), - .SIZE(SIZE), - .BUFFERED(0), - .RWCHECK(1), - .FASTRAM(FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .BUFFERED (0), + .RWCHECK (1), + .FASTRAM (FASTRAM) ) dp_ram ( .clk(clk), .waddr(wr_ptr_r), diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index 2bf19ce1..b39c71cf 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -212,7 +212,9 @@ "miss_st0": 1, "force_miss_st0": 1, "mshr_push": 1, - "?pipeline_stall": 1 + "?crsq_alm_full": 1, + "?dreq_alm_full": 1, + "?mshr_alm_full": 1 } } }