code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/libs/VX_skid_buffer.v
+++ b/hw/rtl/libs/VX_skid_buffer.v
@@ -30,9 +30,7 @@ module VX_skid_buffer #(

    end else if (NOBACKPRESSURE) begin

-        always @(posedge clk) begin
-            assert(ready_out) else $error("ready_out should always be asserted");
-        end
+        `RUNTIME_ASSERT(ready_out, ("ready_out should always be asserted"))

        wire stall = valid_out && ~ready_out;