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code refactoring for Vivado, sv2v, and yosys compatibility

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Blaise Tine
2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
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4
hw/rtl/libs/VX_index_buffer.v
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@@ -55,10 +55,10 @@ module VX_index_buffer #(
full_r <= 1'b0;
end else begin
if (release_slot) begin
assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
`ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid slot at port %d", $time, release_addr));
end
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
`ASSERT(1 == free_slots[write_addr], ("%t: acquiring used slot at port %d", $time, write_addr));
end
write_addr_r <= free_index;
free_slots <= free_slots_n;