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code refactoring for Vivado, sv2v, and yosys compatibility

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This commit is contained in:
Blaise Tine
2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
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59
hw/rtl/libs/VX_axi_adapter.v
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@@ -1,15 +1,15 @@
`include "VX_define.vh"
module VX_axi_adapter #(
parameter VX_DATA_WIDTH = 512,
parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)),
parameter VX_TAG_WIDTH = 8,
parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
parameter VX_DATA_WIDTH = 512,
parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)),
parameter VX_TAG_WIDTH = 8,
parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
parameter VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
) (
input wire clk,
input wire reset,
@@ -29,8 +29,7 @@ module VX_axi_adapter #(
output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_req_ready,
// AXI write address channel
output wire m_axi_awvalid,
// AXI write request address channel
output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
@@ -39,18 +38,24 @@ module VX_axi_adapter #(
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire [3:0] m_axi_awqos,
output wire [3:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// AXI write data channel
output wire m_axi_wvalid,
// AXI write request data channel
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// AXI write response channel
input wire [AXI_TID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// AXI read address channel
output wire m_axi_arvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
@@ -60,12 +65,15 @@ module VX_axi_adapter #(
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire [3:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// AXI read data channel
input wire m_axi_rvalid,
// AXI read response channel
input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam AXSIZE = $clog2(VX_DATA_WIDTH/8);
@@ -73,6 +81,8 @@ module VX_axi_adapter #(
`STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter"))
`STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter"))
//`UNUSED_VAR ()
reg awvalid_ack;
reg wvalid_ack;
@@ -95,7 +105,7 @@ module VX_axi_adapter #(
wire axi_write_ready = (m_axi_awready || awvalid_ack) && (m_axi_wready || wvalid_ack);
// AXI write address channel
// AXI write request address channel
assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack;
assign m_axi_awid = mem_req_tag;
assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
@@ -107,13 +117,18 @@ module VX_axi_adapter #(
assign m_axi_awprot = 3'b0;
assign m_axi_awqos = 4'b0;
// AXI write data channel
// AXI write request data channel
assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack;
assign m_axi_wdata = mem_req_data;
assign m_axi_wstrb = mem_req_byteen;
assign m_axi_wlast = 1'b1;
// AXI read address channel
// AXI write response channel
`UNUSED_VAR (m_axi_bid);
`RUNTIME_ASSERT(~m_axi_bvalid || m_axi_bresp == 0, ("AXI response error"));
assign m_axi_bready = 1'b1;
// AXI read request channel
assign m_axi_arvalid = mem_req_valid && !mem_req_rw;
assign m_axi_arid = mem_req_tag;
assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
@@ -125,10 +140,12 @@ module VX_axi_adapter #(
assign m_axi_arprot = 3'b0;
assign m_axi_arqos = 4'b0;
// AXI read data channel
// AXI read response channel
assign mem_rsp_valid = m_axi_rvalid;
assign mem_rsp_tag = m_axi_rid;
assign mem_rsp_data = m_axi_rdata;
`RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("AXI response error"));
`UNUSED_VAR (m_axi_rlast);
assign m_axi_rready = mem_rsp_ready;
// Vortex request ack

2
hw/rtl/libs/VX_bypass_buffer.v
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@@ -31,7 +31,7 @@ module VX_bypass_buffer #(
buffer_valid <= 0;
end
if (valid_in && ~ready_out) begin
assert(!buffer_valid);
`ASSERT(!buffer_valid, "runtime error");
buffer_valid <= 1;
end
end

4
hw/rtl/libs/VX_dp_ram.v
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@@ -28,7 +28,9 @@ module VX_dp_ram #(
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
initial \
for (integer i = 0; i < SIZE; ++i)\
ram[i] = INIT_VALUE; \
end \
end

8
hw/rtl/libs/VX_fifo_queue.v
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@@ -35,8 +35,8 @@ module VX_fifo_queue #(
head_r <= 0;
size_r <= 0;
end else begin
assert(!push || !full);
assert(!pop || !empty);
`ASSERT(!push || !full, ("runtime error"));
`ASSERT(!pop || !empty, ("runtime error"));
if (push) begin
if (!pop) begin
size_r <= 1;
@@ -71,8 +71,8 @@ module VX_fifo_queue #(
alm_full_r <= 0;
used_r <= 0;
end else begin
assert(!push || !full);
assert(!pop || !empty);
`ASSERT(!push || !full, ("runtime error"));
`ASSERT(!pop || !empty, ("runtime error"));
if (push) begin
if (!pop) begin
empty_r <= 0;

2
hw/rtl/libs/VX_find_first.v
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@@ -5,7 +5,7 @@ module VX_find_first #(
parameter N = 1,
parameter DATAW = 1,
parameter REVERSE = 0,
localparam LOGN = $clog2(N)
parameter LOGN = $clog2(N)
) (
input wire [N-1:0][DATAW-1:0] data_i,
input wire [N-1:0] valid_i,

4
hw/rtl/libs/VX_index_buffer.v
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@@ -55,10 +55,10 @@ module VX_index_buffer #(
full_r <= 1'b0;
end else begin
if (release_slot) begin
assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
`ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid slot at port %d", $time, release_addr));
end
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
`ASSERT(1 == free_slots[write_addr], ("%t: acquiring used slot at port %d", $time, write_addr));
end
write_addr_r <= free_index;
free_slots <= free_slots_n;

6
hw/rtl/libs/VX_index_queue.v
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@@ -32,10 +32,8 @@ module VX_index_queue #(
assign enqueue = push;
assign dequeue = !empty && !valid[rd_a]; // auto-remove when head is invalid
always @(*) begin
assert(!push || !full);
end
`RUNTIME_ASSERT(!push || !full, ("invalid inputs"));
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 0;

6
hw/rtl/libs/VX_lzc.v
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@@ -2,9 +2,9 @@
`TRACING_OFF
module VX_lzc #(
parameter N = 2,
parameter MODE = 0, // 0 -> trailing zero, 1 -> leading zero
localparam LOGN = $clog2(N)
parameter N = 2,
parameter MODE = 0, // 0 -> trailing zero, 1 -> leading zero
parameter LOGN = $clog2(N)
) (
input wire [N-1:0] in_i,
output wire [LOGN-1:0] cnt_o,

2
hw/rtl/libs/VX_pending_size.v
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@@ -25,7 +25,7 @@ module VX_pending_size #(
empty_r <= 1;
full_r <= 0;
end else begin
assert(!incr || !full);
`ASSERT(!incr || !full, ("runtime error"));
if (incr) begin
if (!decr) begin
empty_r <= 0;

4
hw/rtl/libs/VX_skid_buffer.v
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@@ -30,9 +30,7 @@ module VX_skid_buffer #(
end else if (NOBACKPRESSURE) begin
always @(posedge clk) begin
assert(ready_out) else $error("ready_out should always be asserted");
end
`RUNTIME_ASSERT(ready_out, ("ready_out should always be asserted"))
wire stall = valid_out && ~ready_out;

4
hw/rtl/libs/VX_sp_ram.v
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@@ -27,7 +27,9 @@ module VX_sp_ram #(
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
initial \
for (integer i = 0; i < SIZE; ++i)\
ram[i] = INIT_VALUE; \
end \
end

2
hw/rtl/libs/VX_stream_demux.v
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@@ -5,7 +5,7 @@ module VX_stream_demux #(
parameter LANES = 1,
parameter DATAW = 1,
parameter BUFFERED = 0,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,