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code refactoring for Vivado, sv2v, and yosys compatibility

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This commit is contained in:
Blaise Tine
2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
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28
hw/rtl/interfaces/VX_perf_pipeline_if.v
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@@ -4,15 +4,41 @@
`include "VX_define.vh"
interface VX_perf_pipeline_if ();
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] lsu_stalls;
wire [`PERF_CTR_BITS-1:0] csr_stalls;
wire [`PERF_CTR_BITS-1:0] alu_stalls;
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
`ifdef EXT_F_ENABLE
wire [`PERF_CTR_BITS-1:0] fpu_stalls;
`endif
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
modport master (
output ibf_stalls,
output scb_stalls,
output lsu_stalls,
output csr_stalls,
output alu_stalls,
`ifdef EXT_F_ENABLE
output fpu_stalls,
`endif
output gpu_stalls
);
modport slave (
input ibf_stalls,
input scb_stalls,
input lsu_stalls,
input csr_stalls,
input alu_stalls,
`ifdef EXT_F_ENABLE
input fpu_stalls,
`endif
input gpu_stalls
);
endinterface
`endif