code refactoring for Vivado, sv2v, and yosys compatibility

hw/rtl/interfaces/VX_perf_cache_if.v

@@ -14,6 +14,28 @@ interface VX_perf_cache_if ();
     wire [`PERF_CTR_BITS-1:0] pipe_stalls;
     wire [`PERF_CTR_BITS-1:0] crsp_stalls;
 
+    modport master (
+        output reads,
+        output writes,
+        output read_misses,
+        output write_misses,
+        output bank_stalls,
+        output mshr_stalls,
+        output pipe_stalls,
+        output crsp_stalls
+    );
+
+    modport slave (
+        input reads,
+        input writes,
+        input read_misses,
+        input write_misses,
+        input bank_stalls,
+        input mshr_stalls,
+        input pipe_stalls,
+        input crsp_stalls
+    );
+
 endinterface
 
 `endif