code refactoring for Vivado, sv2v, and yosys compatibility

hw/rtl/interfaces/VX_gpu_req_if.v

@@ -20,6 +20,36 @@ interface VX_gpu_req_if();
     
     wire                    ready;
 
+    modport master (
+        output valid,
+        output wid,
+        output tmask,
+        output PC,
+        output next_PC,
+        output op_type,
+        output tid,
+        output rs1_data,
+        output rs2_data,
+        output rd,
+        output wb,    
+        input  ready
+    );
+
+    modport slave (
+        input  valid,
+        input  wid,
+        input  tmask,
+        input  PC,
+        input  next_PC,
+        input  op_type,
+        input  tid,
+        input  rs1_data,
+        input  rs2_data,
+        input  rd,
+        input  wb,    
+        output ready
+    );
+
 endinterface
 
 `endif