code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/interfaces/VX_gpr_rsp_if.v
+++ b/hw/rtl/interfaces/VX_gpr_rsp_if.v
@@ -9,6 +9,18 @@ interface VX_gpr_rsp_if ();
    wire [`NUM_THREADS-1:0][31:0] rs2_data;
    wire [`NUM_THREADS-1:0][31:0] rs3_data;

+    modport master (
+        output rs1_data,
+        output rs2_data,
+        output rs3_data
+    );
+
+    modport slave (
+        input rs1_data,
+        input rs2_data,
+        input rs3_data
+    );
+
 endinterface

 `endif