code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/interfaces/VX_fpu_to_csr_if.v
+++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.v
@@ -12,6 +12,22 @@ interface VX_fpu_to_csr_if ();
    wire [`NW_BITS-1:0]  read_wid;
    wire [`INST_FRM_BITS-1:0] read_frm;

+    modport master (
+        output write_enable,
+        output write_wid,
+        output write_fflags,
+        output read_wid,
+        input  read_frm
+    );
+
+    modport slave (
+        input  write_enable,
+        input  write_wid,
+        input  write_fflags,
+        input  read_wid,
+        output read_frm
+    );
+
 endinterface

 `endif