code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/interfaces/VX_commit_if.v
+++ b/hw/rtl/interfaces/VX_commit_if.v
@@ -13,7 +13,31 @@ interface VX_commit_if ();
    wire [`NR_BITS-1:0]     rd;
    wire                    wb;
    wire                    eop;
-    wire                    ready;  
+    wire                    ready;
+
+    modport master (
+        output valid,
+        output wid,
+        output tmask,
+        output PC,
+        output data,
+        output rd,
+        output wb,
+        output eop,
+        input  ready
+    );
+
+    modport slave (
+        input  valid,
+        input  wid,
+        input  tmask,
+        input  PC,
+        input  data,
+        input  rd,
+        input  wb,
+        input  eop,
+        output ready
+    );

 endinterface