code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/cache/VX_data_access.v
+++ b/hw/rtl/cache/VX_data_access.v
@@ -16,7 +16,7 @@ module VX_data_access #(
    // Enable cache writeable
    parameter WRITE_ENABLE      = 1,

-    localparam WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS)
+    parameter WORD_SELECT_BITS  = `UP(`WORD_SELECT_BITS)
 ) (
    input wire                          clk,
    input wire                          reset,