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code refactoring for Vivado, sv2v, and yosys compatibility

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This commit is contained in:
Blaise Tine
2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
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4
hw/rtl/afu/VX_avs_wrapper.v
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@@ -8,8 +8,8 @@ module VX_avs_wrapper #(
parameter REQ_TAG_WIDTH = 1,
parameter RD_QUEUE_SIZE = 1,
localparam AVS_BYTEENW = (AVS_DATA_WIDTH / 8),
localparam RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1)
parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8),
parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1)
) (
input wire clk,
input wire reset,

2
hw/rtl/afu/vortex_afu.sv
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@@ -851,7 +851,7 @@ begin
cci_wr_req_data <= t_ccip_clData'(cci_mem_rsp_data);
if (cci_wr_req_fire) begin
assert(cci_wr_req_ctr != 0);
`ASSERT(cci_wr_req_ctr != 0, ("runtime error"));
cci_wr_req_ctr <= cci_wr_req_ctr - CCI_ADDR_WIDTH'(1);
if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin
cci_wr_req_done <= 1;