code refactoring for Vivado, sv2v, and yosys compatibility

hw/rtl/VX_fetch.v

@@ -9,23 +9,23 @@ module VX_fetch #(
     input wire reset,
 
     // Icache interface
-    VX_icache_req_if    icache_req_if,
-    VX_icache_rsp_if    icache_rsp_if,
+    VX_icache_req_if.master icache_req_if,
+    VX_icache_rsp_if.slave  icache_rsp_if,
 
     // inputs
-    VX_wstall_if        wstall_if,
-    VX_join_if          join_if,
-    VX_branch_ctl_if    branch_ctl_if,
-    VX_warp_ctl_if      warp_ctl_if,
+    VX_wstall_if.slave      wstall_if,
+    VX_join_if.slave        join_if,
+    VX_branch_ctl_if.slave  branch_ctl_if,
+    VX_warp_ctl_if.slave    warp_ctl_if,
 
     // outputs
-    VX_ifetch_rsp_if    ifetch_rsp_if,
+    VX_ifetch_rsp_if.master ifetch_rsp_if,
 
     // csr interface
-    VX_fetch_to_csr_if  fetch_to_csr_if,
+    VX_fetch_to_csr_if.master fetch_to_csr_if,
 
     // busy status
-    output wire         busy
+    output wire             busy
 );
 
     VX_ifetch_req_if  ifetch_req_if();