code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/VX_decode.v
+++ b/hw/rtl/VX_decode.v
@@ -19,12 +19,12 @@ module VX_decode  #(
    input  wire         reset,

    // inputs
-    VX_ifetch_rsp_if    ifetch_rsp_if,
+    VX_ifetch_rsp_if.slave ifetch_rsp_if,

    // outputs      
-    VX_decode_if        decode_if,
-    VX_wstall_if        wstall_if,
-    VX_join_if          join_if
+    VX_decode_if.master decode_if,
+    VX_wstall_if.master wstall_if,
+    VX_join_if.master   join_if
 );
    `UNUSED_PARAM (CORE_ID)
    `UNUSED_VAR (clk)