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instruction decode optimization

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This commit is contained in:
Blaise Tine
2021-02-14 00:19:54 -08:00
parent 3c37db877a
commit 9eed48435c
2 changed files with 33 additions and 18 deletions
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2
hw/rtl/cache/VX_bank.v vendored
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@@ -352,7 +352,7 @@ module VX_bank #(
|| incoming_fill_st1;
wire send_fill_req_st1 = !is_fill_st1 && !mem_rw_st1 && miss_st1
&& (!force_miss_st1 || (is_mshr_st1 && !prev_miss_dep_st1))
&& (!force_miss_st1 || (!IN_ORDER_DRAM && is_mshr_st1 && !prev_miss_dep_st1))
&& !incoming_fill_qual_st1;
wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1;