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Vector changes

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This commit is contained in:
proshan3
2019-11-21 17:07:49 -05:00
parent 629f376551
commit 9edb7fe76c
14 changed files with 4927 additions and 3941 deletions
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12
runtime/mains/vector_test/Makefile
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@@ -1,10 +1,13 @@
COMP = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-gcc COMP = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-gcc
CC_FLAGS = -ffreestanding -O0 -Wl,--gc-sections -nostartfiles -nostdlib -nostartfiles -nodefaultlibs -Wl,-Bstatic,-T,../vortex_link.ld -march=rv32imv -mabi=ilp32 CC_FLAGS = -ffreestanding -O0 -Wl,--gc-sections -nostartfiles -nostdlib -nostartfiles -nodefaultlibs -Wl,-Bstatic,-T,../vortex_link.ld -march=rv32imv -mabi=ilp32
DMP = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-objdump #DMP = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-objdump
CPY = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-objcopy #CPY = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-objcopy
DMP = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-objdump
CPY = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-objcopy
# VX_STR = ../../startup/vx_start.s # VX_STR = ../../startup/vx_start.s
@@ -18,7 +21,8 @@ VX_API = ../../vx_api/vx_api.c
VX_TEST = ../../tests/tests.c VX_TEST = ../../tests/tests.c
VX_FIO = ../../fileio/fileio.s VX_FIO = ../../fileio/fileio.s
VX_VEC = vx_vec.s VX_VEC = vx_vec.s
LIBS = /home/fares/dev/riscv-gnu-toolchain-vector/drops/riscv32-unknown-elf/lib/libc.a /home/fares/dev/riscv-gnu-toolchain-vector/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc #LIBS = /home/fares/dev/riscv-gnu-toolchain-vector/drops/riscv32-unknown-elf/lib/libc.a /home/fares/dev/riscv-gnu-toolchain-vector/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
LIBS = /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libc.a /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
VX_MAIN = vx_vector_main VX_MAIN = vx_vector_main

8
runtime/mains/vector_test/vx_vec.s
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@@ -4,4 +4,12 @@
.type vx_vec_test, @function .type vx_vec_test, @function
.global vx_vec_test .global vx_vec_test
vx_vec_test: vx_vec_test:
li a0, 2
vsetvli t0, a0, e32, m1
li a0, 10
sw a0, 0(a1)
sw a0, 32(a1)
vlw.v v0, (a1)
vadd.vv v0, v0, v0
vsw.v v0, (a1)
ret ret

7681
runtime/mains/vector_test/vx_vector_main.dump
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runtime/mains/vector_test/vx_vector_main.elf Normal file → Executable file
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runtime/mains/vector_test/vx_vector_main.hex
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2
simX/core.cpp
View File

@@ -640,7 +640,7 @@ Warp::Warp(Core *c, Word id) :
core(c), pc(0x80000000), interruptEnable(true), core(c), pc(0x80000000), interruptEnable(true),
supervisorMode(true), activeThreads(0), reg(0), pred(0), supervisorMode(true), activeThreads(0), reg(0), pred(0),
shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id), shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id),
spawned(false), steps(0), insts(0), loads(0), stores(0) spawned(false), steps(0), insts(0), loads(0), stores(0), VLEN(96)
{ {
D(3, "Creating a new thread with PC: " << hex << this->pc << '\n'); D(3, "Creating a new thread with PC: " << hex << this->pc << '\n');
/* Build the register file. */ /* Build the register file. */

90
simX/enc.cpp
View File

@@ -53,6 +53,8 @@ WordDecoder::WordDecoder(const ArchDef &arch) {
opcode_s = 7; opcode_s = 7;
reg_s = 5; reg_s = 5;
func3_s = 3; func3_s = 3;
mop_s = 3;
vmask_s = 1;
shift_opcode = 0; shift_opcode = 0;
shift_rd = opcode_s; shift_rd = opcode_s;
@@ -63,6 +65,13 @@ WordDecoder::WordDecoder(const ArchDef &arch) {
shift_j_u_immed = opcode_s + reg_s; shift_j_u_immed = opcode_s + reg_s;
shift_s_b_immed = opcode_s + reg_s + func3_s + reg_s + reg_s; shift_s_b_immed = opcode_s + reg_s + func3_s + reg_s + reg_s;
shift_i_immed = opcode_s + reg_s + func3_s + reg_s; shift_i_immed = opcode_s + reg_s + func3_s + reg_s;
shift_vset_immed = opcode_s + reg_s + func3_s + reg_s;
shift_vmask = opcode_s + reg_s + func3_s + reg_s + reg_s;
shift_vmop = opcode_s + reg_s + func3_s + reg_s + reg_s + vmask_s;
shift_vnf = opcode_s + reg_s + func3_s + reg_s + reg_s + vmask_s + mop_s;
shift_func6 = opcode_s + reg_s + func3_s + reg_s + reg_s + 1;
shift_vset = opcode_s + reg_s + func3_s + reg_s + reg_s + 6;
reg_mask = 0x1f; reg_mask = 0x1f;
func3_mask = 0x7; func3_mask = 0x7;
@@ -73,6 +82,8 @@ WordDecoder::WordDecoder(const ArchDef &arch) {
b_immed_mask = 0x1fff; b_immed_mask = 0x1fff;
u_immed_mask = 0xfffff; u_immed_mask = 0xfffff;
j_immed_mask = 0xfffff; j_immed_mask = 0xfffff;
v_immed_mask = 0x7ff;
func6_mask = 0x3f;
} }
@@ -215,7 +226,84 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
trace_inst->rd = ((code>>shift_rd) & reg_mask); trace_inst->rd = ((code>>shift_rd) & reg_mask);
break; break;
defualt:
case InstType::V_TYPE:
cout << "Entered here: instr type = vector" << op << endl;
switch(op) {
case Opcode::VSET_ARITH: //TODO: arithmetic ops
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
func3 = (code>>shift_func3) & func3_mask;
inst.setFunc3 (func3);
cout << "Entered here: instr type = vector" << endl;
if(func3 == 7) {
cout << "Entered here: imm instr";
inst.setVsetImm(!(code>>shift_vset));
if(inst.getVsetImm()) {
Word immed = (code>>shift_rs2) & v_immed_mask;
D(3, "immed" << immed);
inst.setSrcImm(immed); //TODO
inst.setvlmul(immed & 0x3);
D(3, "lmul " << (immed & 0x3));
inst.setvediv((immed>>4) & 0x3);
D(3, "ediv " << ((immed>>4) & 0x3));
inst.setvsew((immed>>2) & 0x3);
D(3, "sew " << ((immed>>2) & 0x3));
}
else {
inst.setSrcReg((code>>shift_rs2) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
}
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
} else {
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask) & 0x1);
inst.setFunc6((code>>shift_func6) & func6_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
}
break;
case Opcode::VL:
D(3, "vector load instr");
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setVlsWidth((code>>shift_func3) & func3_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask));
inst.setVmop((code>>shift_vmop) && func3_mask);
inst.setVnf((code>>shift_vnf) && func3_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
break;
case Opcode::VS:
inst.setVs3((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setVlsWidth((code>>shift_func3) & func3_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask));
inst.setVmop((code>>shift_vmop) && func3_mask);
inst.setVnf((code>>shift_vnf) && func3_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
break;
}
break;
default:
cout << "Unrecognized argument class in word decoder.\n"; cout << "Unrecognized argument class in word decoder.\n";
exit(1); exit(1);
} }

20
simX/include/core.h
View File

@@ -37,6 +37,8 @@ namespace Harp {
public: public:
Reg(): cpuId(0), regNum(0), val(0) {} Reg(): cpuId(0), regNum(0), val(0) {}
Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {} Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {}
Reg(Word c, Word n, T v): cpuId(c), regNum(n), val(v) {}
Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; } Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; }
@@ -47,9 +49,10 @@ namespace Harp {
val &= mask; val &= mask;
} }
T val;
private: private:
Word cpuId, regNum; Word cpuId, regNum;
T val; // T val;
#ifdef EMU_INSTRUMENTATION #ifdef EMU_INSTRUMENTATION
/* Access size here is 8, representing the register size of 64-bit cores. */ /* Access size here is 8, representing the register size of 64-bit cores. */
@@ -86,6 +89,14 @@ namespace Harp {
Word pc; Word pc;
}; };
struct vtype
{
int vill;
int vediv;
int vsew;
int vlmul;
};
class Warp; class Warp;
class Core { class Core {
@@ -172,6 +183,13 @@ namespace Harp {
std::vector<Word> shadowReg; std::vector<Word> shadowReg;
std::vector<bool> shadowPReg; std::vector<bool> shadowPReg;
//Vector CSR
struct vtype vtype; //both of them are XLEN WIDE
int vl; //both of them are XLEN WIDE
Word VLEN; //Total vector length
std::vector<std::vector<Reg<char*>>> vreg; // 32 vector registers
bool interruptEnable, shadowInterruptEnable, supervisorMode, bool interruptEnable, shadowInterruptEnable, supervisorMode,
shadowSupervisorMode, spawned; shadowSupervisorMode, spawned;

4
simX/include/debug.h
View File

@@ -5,14 +5,14 @@
#define __DEBUG_H #define __DEBUG_H
// #define USE_DEBUG 9 // #define USE_DEBUG 9
#define USE_DEBUG -1 #define USE_DEBUG 3
#ifdef USE_DEBUG #ifdef USE_DEBUG
#include <iostream> #include <iostream>
#define D(lvl, x) do { \ #define D(lvl, x) do { \
using namespace std; \ using namespace std; \
if ((lvl) <= USE_DEBUG) { \ if ((lvl) == USE_DEBUG) { \
cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \ cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \
<< x << endl; \ << x << endl; \
} \ } \

6
simX/include/enc.h
View File

@@ -60,11 +60,15 @@ namespace Harp {
Size inst_s, opcode_s, reg_s, func3_s; Size inst_s, opcode_s, reg_s, func3_s;
Size shift_opcode, shift_rd, shift_rs1, shift_rs2, shift_func3, shift_func7; Size shift_opcode, shift_rd, shift_rs1, shift_rs2, shift_func3, shift_func7;
Size shift_j_u_immed, shift_s_b_immed, shift_i_immed; Size shift_j_u_immed, shift_s_b_immed, shift_i_immed;
//Vector
Size shift_vset, shift_vset_immed, shift_vmask, shift_vmop, shift_vnf, shift_func6;
Size vmask_s, mop_s;
Word reg_mask, func3_mask, func7_mask, opcode_mask, i_immed_mask, Word reg_mask, func3_mask, func7_mask, opcode_mask, i_immed_mask,
s_immed_mask, b_immed_mask, u_immed_mask, j_immed_mask; s_immed_mask, b_immed_mask, u_immed_mask, j_immed_mask, v_immed_mask, func6_mask;
}; };

2
simX/include/harpfloat.h
View File

@@ -81,7 +81,7 @@ namespace Harp {
bool sign(d < 0); bool sign(d < 0);
bool inf(isinf(d)), zero(d == 0.0); bool inf(std::isinf(d)), zero(d == 0.0);
int exp; int exp;
if (!inf && !zero) exp = floor(log2(fabs(d))); if (!inf && !zero) exp = floor(log2(fabs(d)));

37
simX/include/instruction.h
View File

@@ -6,6 +6,7 @@
#include <map> #include <map>
#include <iostream> #include <iostream>
#include <math.h>
#include "types.h" #include "types.h"
#include "trace.h" #include "trace.h"
@@ -29,10 +30,13 @@ namespace Harp {
TRAP = 0x7f, TRAP = 0x7f,
FENCE = 0x0f, FENCE = 0x0f,
PJ_INST = 0x7b, PJ_INST = 0x7b,
GPGPU = 0x6b GPGPU = 0x6b,
VSET_ARITH = 0x57,
VL = 0x7,
VS = 0x27,
}; };
enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE}; enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE, V_TYPE};
// We build a table of instruction information out of this. // We build a table of instruction information out of this.
struct InstTableEntry_t { struct InstTableEntry_t {
@@ -58,7 +62,10 @@ namespace Harp {
{Opcode::TRAP, {"TRAP" , true , false, false, false, InstType::I_TYPE }}, {Opcode::TRAP, {"TRAP" , true , false, false, false, InstType::I_TYPE }},
{Opcode::FENCE, {"fence" , true , false, false, false, InstType::I_TYPE }}, {Opcode::FENCE, {"fence" , true , false, false, false, InstType::I_TYPE }},
{Opcode::PJ_INST, {"pred j", true , false, false, false, InstType::R_TYPE }}, {Opcode::PJ_INST, {"pred j", true , false, false, false, InstType::R_TYPE }},
{Opcode::GPGPU, {"gpgpu" , false, false, false, false, InstType::R_TYPE }} {Opcode::GPGPU, {"gpgpu" , false, false, false, false, InstType::R_TYPE }},
{Opcode::VSET_ARITH, {"vsetvl" , false, false, false, false, InstType::V_TYPE }},
{Opcode::VL, {"vl" , false, false, false, false, InstType::V_TYPE }},
{Opcode::VS, {"vs" , false, false, false, false, InstType::V_TYPE }}
}; };
static const Size MAX_REG_SOURCES(3); static const Size MAX_REG_SOURCES(3);
@@ -94,6 +101,16 @@ namespace Harp {
Word *setSrcImm () { immsrcPresent = true; immsrc = 0xa5; return &immsrc;} Word *setSrcImm () { immsrcPresent = true; immsrc = 0xa5; return &immsrc;}
void setSrcImm (Word srcImm) { immsrcPresent = true; immsrc = srcImm; } void setSrcImm (Word srcImm) { immsrcPresent = true; immsrc = srcImm; }
void setImmRef (Ref &r) { refLiteral = &r; } void setImmRef (Ref &r) { refLiteral = &r; }
void setVsetImm (Word vset_imm) { if(vset_imm) vsetImm = true; else vsetImm = false; }
void setVlsWidth (Word width) { vlsWidth = width; }
void setVmop( Word mop) { vMop = mop; }
void setVnf(Word nf) { vNf = nf; }
void setVmask(Word mask) { vmask = mask; }
void setVs3(Word vs) { vs3 = vs; }
void setvlmul(Word lmul) { vlmul = pow(2, lmul); }
void setvsew(Word sew) { vsew = pow(2, 3+sew); }
void setvediv(Word ediv) { vediv = pow(2,ediv); }
void setFunc6(Word func6) { this->func6 = func6; }
/* Getters used by encoders. */ /* Getters used by encoders. */
Opcode getOpcode() const { return op; } Opcode getOpcode() const { return op; }
@@ -111,6 +128,16 @@ namespace Harp {
Word getImm() const { return immsrc; } Word getImm() const { return immsrc; }
bool hasRefLiteral() const { return refLiteral != NULL; } bool hasRefLiteral() const { return refLiteral != NULL; }
Ref *getRefLiteral() const { return refLiteral; } Ref *getRefLiteral() const { return refLiteral; }
bool getVsetImm() const { return vsetImm; }
Word getVlsWidth() const { return vlsWidth; }
Word getVmop() const { return vMop; }
Word getvNf() const { return vNf; }
bool getVmask() const { return vmask; }
Word getVs3() const { return vs3; }
Word getvlmul() const { return vlmul; }
Word getvsew() const { return vsew; }
Word getvediv() const { return vediv; }
/* Getters used as table lookup. */ /* Getters used as table lookup. */
bool hasRelImm() const { return (*(instTable.find(op))).second.relAddress; } bool hasRelImm() const { return (*(instTable.find(op))).second.relAddress; }
@@ -129,6 +156,10 @@ namespace Harp {
RegNum rdest, pdest; RegNum rdest, pdest;
Ref *refLiteral; Ref *refLiteral;
//Vector
bool vsetImm, vmask;
Word vlsWidth, vMop, vNf, vs3, vlmul, vsew, vediv, func6;
public: public:

498
simX/instruction.cpp
View File

@@ -358,12 +358,14 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
} }
bool is_vec = false;
Size nextActiveThreads = c.activeThreads; Size nextActiveThreads = c.activeThreads;
Size wordSz = c.core->a.getWordSize(); Size wordSz = c.core->a.getWordSize();
Word nextPc = c.pc; Word nextPc = c.pc;
Word VLMAX;
c.memAccesses.clear(); c.memAccesses.clear();
@@ -1085,6 +1087,502 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
cout << "ERROR: UNSUPPORTED GPGPU INSTRUCTION " << *this << "\n"; cout << "ERROR: UNSUPPORTED GPGPU INSTRUCTION " << *this << "\n";
} }
break; break;
case VSET_ARITH:
D(3,"VSET_ARITH");
is_vec = true;
switch(func3) {
case 0: // vector-vector
switch(func6)
{
case 0:
{
is_vec = true;
D(3, "Addition " << rsrc[0] << " " << rsrc[1] << " Dest:" << rdest);
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if (c.vtype.vsew == 8)
{
} else if (c.vtype.vsew == 16)
{
} else if (c.vtype.vsew == 32)
{
cout << "Doing 32 bit vector addition\n";
for (Word i = 0; i < c.vl; i++)
{
int * first_ptr = (int *) vr1[i].val;
int * second_ptr = (int *) vr2[i].val;
int result = *first_ptr + *second_ptr;
cout << "Adding " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int * result_ptr = (int *) vd[i].val;
*result_ptr = result;
}
}
D(3, "Vector Register state after addition:");
for(int i=0; i < c.vreg.size(); i++)
for(int j=0; j< c.vreg[0].size(); j++)
{
if (c.vtype.vsew == 8)
{
uint8_t * ptr_val = (uint8_t *) c.vreg[i][j].val;
std::cout << "reg[" << i << "][" << j << "] = " << *ptr_val << std::endl;
} else if (c.vtype.vsew == 16)
{
uint16_t * ptr_val = (uint16_t *) c.vreg[i][j].val;
std::cout << "reg[" << i << "][" << j << "] = " << *ptr_val << std::endl;
} else if (c.vtype.vsew == 32)
{
uint32_t * ptr_val = (uint32_t *) c.vreg[i][j].val;
std::cout << "reg[" << i << "][" << j << "] = " << *ptr_val << std::endl;
}
}
}
break;
case 24: //vmseq
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr == *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint8_t * result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr == *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint16_t * result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr == *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint32_t * result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 25: //vmsne
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr != *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint8_t * result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr != *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint16_t * result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr != *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint32_t * result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 26: //vmsltu
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr < *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint8_t * result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr < *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint16_t * result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr < *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint32_t * result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 27: //vmslt
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(int8_t i = 0; i < c.vl; i++){
int8_t *first_ptr = (int8_t *)vr1[i].val;
int8_t *second_ptr = (int8_t *)vr2[i].val;
int8_t result = (*first_ptr < *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int8_t * result_ptr = (int8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(int16_t i = 0; i < c.vl; i++){
int16_t *first_ptr = (int16_t *)vr1[i].val;
int16_t *second_ptr = (int16_t *)vr2[i].val;
int16_t result = (*first_ptr < *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int16_t * result_ptr = (int16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(int32_t i = 0; i < c.vl; i++){
int32_t *first_ptr = (int32_t *)vr1[i].val;
int32_t *second_ptr = (int32_t *)vr2[i].val;
int32_t result = (*first_ptr < *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int32_t * result_ptr = (int32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 28: //vmsleu
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr <= *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint8_t * result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr <= *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint16_t * result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr <= *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint32_t * result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 29: //vmsle
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(int8_t i = 0; i < c.vl; i++){
int8_t *first_ptr = (int8_t *)vr1[i].val;
int8_t *second_ptr = (int8_t *)vr2[i].val;
int8_t result = (*first_ptr <= *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int8_t * result_ptr = (int8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(int16_t i = 0; i < c.vl; i++){
int16_t *first_ptr = (int16_t *)vr1[i].val;
int16_t *second_ptr = (int16_t *)vr2[i].val;
int16_t result = (*first_ptr <= *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int16_t * result_ptr = (int16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(int32_t i = 0; i < c.vl; i++){
int32_t *first_ptr = (int32_t *)vr1[i].val;
int32_t *second_ptr = (int32_t *)vr2[i].val;
int32_t result = (*first_ptr <= *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int32_t * result_ptr = (int32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 30: //vmsgtu
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr > *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint8_t * result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr > *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint16_t * result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr > *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
uint32_t * result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
case 31: //vmsgt
{
vector<Reg<char *>> vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(int8_t i = 0; i < c.vl; i++){
int8_t *first_ptr = (int8_t *)vr1[i].val;
int8_t *second_ptr = (int8_t *)vr2[i].val;
int8_t result = (*first_ptr > *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int8_t * result_ptr = (int8_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 16) {
for(int16_t i = 0; i < c.vl; i++){
int16_t *first_ptr = (int16_t *)vr1[i].val;
int16_t *second_ptr = (int16_t *)vr2[i].val;
int16_t result = (*first_ptr > *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int16_t * result_ptr = (int16_t *) vd[i].val;
*result_ptr = result;
}
} else if(c.vtype.vsew == 32) {
for(int32_t i = 0; i < c.vl; i++){
int32_t *first_ptr = (int32_t *)vr1[i].val;
int32_t *second_ptr = (int32_t *)vr2[i].val;
int32_t result = (*first_ptr > *second_ptr) ? 1 : 0;
cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n';
int32_t * result_ptr = (int32_t *) vd[i].val;
*result_ptr = result;
}
}
}
break;
}
break;
case 7:
{
is_vec = true;
c.vtype.vill = 0; //TODO
c.vtype.vediv = vediv;
c.vtype.vsew = vsew;
c.vtype.vlmul = vlmul;
D(3, "lmul:" << vlmul << " sew:" << vsew << " ediv: " << vediv);
Word VLMAX = (vlmul * c.VLEN)/vsew;
if(reg[rsrc[0]] <= VLMAX){
c.vl = reg[rsrc[0]];
}
if(reg[rsrc[0]] >= (2*VLMAX)) {
c.vl = VLMAX;
}
reg[rdest] = c.vl;
D(3, "VL:" << reg[rdest]);
Word regNum(0);
for (int j = 0; j < 32; j++)
{
c.vreg.push_back(vector<Reg<char*>>());
for (int i = 0; i < (c.VLEN/vsew); ++i)
{
int * elem_ptr = (int *) malloc(vsew/8);
for (int f = 0; f < (vsew/32); f++) elem_ptr[f] = 1;
c.vreg[j].push_back(Reg<char*>(c.id, regNum++, (char *) elem_ptr));
}
}
}
break;
}
break;
case VL:
{
is_vec = true;
D(3, "Executing vector load");
VLMAX = (c.vtype.vlmul * c.VLEN)/c.vtype.vsew;
D(3, "lmul: " << c.vtype.vlmul << " VLEN:" << c.VLEN << "sew: " << c.vtype.vsew);
D(3, "src: " << rsrc[0] << " " << reg[rsrc[0]]);
D(3, "dest" << rdest);
D(3, "width" << vlsWidth);
vector<Reg<char *>> vd = c.vreg[rdest];
switch(vlsWidth) {
case 6: //load word and unit strided (not checking for unit stride)
for(Word i = 0; i < c.vl; i++) {
memAddr = ((reg[rsrc[0]]) & 0xFFFFFFFC) + i*c.vtype.vsew;
data_read = c.core->mem.read(memAddr, c.supervisorMode);
D(3, "Data read " << data_read);
int * result_ptr = (int *) vd[i].val;
*result_ptr = data_read;
//trace_inst->is_lw = true;
//trace_inst->mem_addresses[t] = memAddr;
}
for(Word i = c.vl; i < VLMAX; i++){
int * result_ptr = (int *) vd[i].val;
*result_ptr = 0;
}
D(3, "Vector Register state after addition:");
for(int i=0; i < c.vreg.size(); i++)
for(int j=0; j< c.vreg[0].size(); j++)
{
if (c.vtype.vsew == 8)
{
uint8_t * ptr_val = (uint8_t *) c.vreg[i][j].val;
std::cout << "reg[" << i << "][" << j << "] = " << *ptr_val << std::endl;
} else if (c.vtype.vsew == 16)
{
uint16_t * ptr_val = (uint16_t *) c.vreg[i][j].val;
std::cout << "reg[" << i << "][" << j << "] = " << *ptr_val << std::endl;
} else if (c.vtype.vsew == 32)
{
uint32_t * ptr_val = (uint32_t *) c.vreg[i][j].val;
std::cout << "reg[" << i << "][" << j << "] = " << *ptr_val << std::endl;
}
}
break;
}
}
break;
case VS:
is_vec = true;
VLMAX = (c.vtype.vlmul * c.VLEN)/c.vtype.vsew;
for(Word i = 0; i < c.vl; i++) {
++c.stores;
memAddr = reg[rsrc[0]] + i*c.vtype.vsew;
std::cout << "STORE MEM ADDRESS: " << std::hex << memAddr << "\n";
//trace_inst->is_sw = true;
//trace_inst->mem_addresses[t] = memAddr;
switch (vlsWidth)
{
case 6: //store word and unit strided (not checking for unit stride)
{
uint32_t * ptr_val = (uint32_t *) c.vreg[vs3][i].val;
c.core->mem.write(memAddr, *ptr_val, c.supervisorMode, 4);
D(3, "store: " << memAddr << " value:" << *ptr_val);
}
break;
default:
cout << "ERROR: UNSUPPORTED S INST\n";
exit(1);
}
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
}
break;
default: default:
cout << "pc: " << hex << (c.pc-4) << "\n"; cout << "pc: " << hex << (c.pc-4) << "\n";
cout << "aERROR: Unsupported instruction: " << *this << "\n" << flush; cout << "aERROR: Unsupported instruction: " << *this << "\n" << flush;

2
simX/test_riscv.sh Normal file → Executable file
View File

@@ -3,4 +3,4 @@ echo start > results.txt
# echo ../kernel/vortex_test.hex # echo ../kernel/vortex_test.hex
make make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n" printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/fares/Desktop/Vortex/rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/vector_test/vx_vector_main.hex -s -b 1> emulator.debug