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Merge remote-tracking branch 'origin/tensor_core' into rtl

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Hansung Kim
2024-05-05 17:03:57 -07:00
parent 1c7acab160 5bd25985c6
commit 9ea291eea2
16 changed files with 880 additions and 24 deletions
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13
hw/rtl/core/VX_commit.sv
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@@ -54,6 +54,7 @@ module VX_commit import VX_gpu_pkg::*; #(
wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] commit_tmask;
wire [`ISSUE_WIDTH-1:0] commit_eop;
wire [`ISSUE_WIDTH-1:0][`EX_BITS-1:0] commit_sel;
`UNUSED_VAR (commit_sel)
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
@@ -176,14 +177,17 @@ module VX_commit import VX_gpu_pkg::*; #(
// relies on 1 cycle delay of arbiter and continuous issuing of tensor instructions,
// so probably want to change this at some point
// (i.e. pass a "don't count this towards pending instructions" signal down the pipeline)
logic [`ISSUE_WIDTH-1:0][4:0] hmma_ctr, hmma_ctr_n;
// logic [`ISSUE_WIDTH-1:0][4:0] hmma_ctr, hmma_ctr_n;
wire [`ISSUE_WIDTH-1:0] final_hmma;
`ifdef EXT_T_ENABLE
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
assign hmma_ctr_n[i] = (tensor_commit_if[i].valid && tensor_commit_if[i].ready) ? hmma_ctr[i] + 5'b1 : hmma_ctr[i];
assign final_hmma[i] = (commit_sel[i] != `EX_BITS'(2) || hmma_ctr == '0);
// assign hmma_ctr_n[i] = (tensor_commit_if[i].valid && tensor_commit_if[i].ready) ? hmma_ctr[i] + 5'b1 : hmma_ctr[i];
// assign final_hmma[i] = (commit_sel[i] != `EX_BITS'(2) || hmma_ctr == '0);
// i suppose this is now a feature and not a bug
// if PC is 0, this means it is not final step of a wmma, shouldn't be committed
assign final_hmma[i] = (commit_if[i].data.PC != 32'b0);
end
/*
always @(posedge clk) begin
if (reset) begin
hmma_ctr <= '0;
@@ -192,6 +196,7 @@ module VX_commit import VX_gpu_pkg::*; #(
hmma_ctr <= hmma_ctr_n;
end
end
*/
`else
assign final_hmma = '1;
`endif

17
hw/rtl/core/VX_operands.sv
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@@ -306,15 +306,14 @@ module VX_operands import VX_gpu_pkg::*; #(
cycle <= cycle_n;
end
if (cycle == 32'd25000) begin
for (integer k = 0; k < `NUM_REGS * ISSUE_RATIO; ++k) begin
$display("warp %0d, thread %0d, register %0d: %0x",
i * ISSUE_RATIO + (k / `NUM_REGS),
j,
k % `NUM_REGS,
gpr_ram.ram[k]);
end
end
// if (cycle == 32'd25000) begin
// for (integer k = 0; k < `NUM_REGS * ISSUE_RATIO; ++k) begin
// integer warp = i * ISSUE_RATIO + (k / `NUM_REGS);
// integer thread = j;
// integer register = k % `NUM_REGS;
// $display("warp %0d, thread %0d, register %0d: %0x", warp, thread, register, gpr_ram.ram[k]);
// end
// end
end
end
end

9
hw/rtl/core/VX_tensor_core.sv
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@@ -58,7 +58,8 @@ module VX_tensor_core_warp import VX_gpu_pkg::*; #(
logic result_valid;
logic result_ready;
VX_tensor_octet #(
.ISW(ISW),
.OCTET(i)
) octet (
.clk(clk),
.reset(reset),
@@ -180,7 +181,8 @@ module VX_tensor_core_warp import VX_gpu_pkg::*; #(
endmodule
module VX_tensor_octet #(
parameter ISW,
parameter OCTET
) (
input clk,
input reset,
@@ -285,7 +287,8 @@ module VX_tensor_octet #(
wire do_hmma = (substep == 1'b1 && operands_valid && operands_ready);
VX_tensor_dpu #(
.ISW(ISW),
.OCTET(OCTET)
) dpu (
.clk(clk),
.reset(reset),

2
hw/rtl/core/VX_tensor_ucode.vh
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@@ -92,5 +92,5 @@ HMMA_SET3_STEP3_0: begin
uop = {NEXT, HMMA_SET3_STEP3_1, `EX_BITS'(`EX_TENSOR), `INST_OP_BITS'(3), `INST_MOD_BITS'(0), 1'b1, 1'b0, 1'b0, 32'b0, 32'b0, `FREG(22), `FREG(6), `FREG(14), `FREG(22)};
end
HMMA_SET3_STEP3_1: begin
uop = {FINISH, HMMA_SET0_STEP0_0, `EX_BITS'(`EX_TENSOR), `INST_OP_BITS'(3), `INST_MOD_BITS'(1), 1'b1, 1'b0, 1'b0, 32'b0, 32'b0, `FREG(23), `FREG(7), `FREG(15), `FREG(23)};
uop = {FINISH, HMMA_SET0_STEP0_0, `EX_BITS'(`EX_TENSOR), `INST_OP_BITS'(3), `INST_MOD_BITS'(1), 1'b1, 1'b0, 1'b0, 32'b1, 32'b1, `FREG(23), `FREG(7), `FREG(15), `FREG(23)};
end

8
hw/rtl/core/VX_uop_sequencer.sv
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@@ -125,16 +125,16 @@ module VX_uop_sequencer import VX_gpu_pkg::*; (
always @(posedge clk) begin
if (uop_start) begin
$display("UOP start @ %t", $time);
$display("use_uop=%0d, use_uop_1d=%0d, uop_start=%0d, ibuffer_if.valid=%0d, ibuffer_if.ready=%0d", use_uop, use_uop_1d, uop_start, ibuffer_if.valid, ibuffer_if.ready);
// $display("UOP start @ %t", $time);
// $display("use_uop=%0d, use_uop_1d=%0d, uop_start=%0d, ibuffer_if.valid=%0d, ibuffer_if.ready=%0d", use_uop, use_uop_1d, uop_start, ibuffer_if.valid, ibuffer_if.ready);
end
if (uop_fire) begin
$display("UOP fire @ %t", $time);
// $display("UOP fire @ %t", $time);
end
if (uop_finish) begin
$display("UOP finish @ %t", $time);
// $display("UOP finish @ %t", $time);
end
if (reset) begin

6
hw/rtl/core/generate_ucode.py
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@@ -55,17 +55,21 @@ with open('VX_tensor_ucode.vh', 'w') as f:
finish = (next_sequence_num == 0)
name = "HMMA_SET{}_STEP{}_{}"
ucode = "{}, HMMA_SET{}_STEP{}_{}, `EX_BITS'(`EX_TENSOR), `INST_OP_BITS'({}), `INST_MOD_BITS'({}), 1'b1, 1'b0, 1'b0, 32'b0, 32'b0, `FREG({}), `FREG({}), `FREG({}), `FREG({})"
ucode = "{}, HMMA_SET{}_STEP{}_{}, `EX_BITS'(`EX_TENSOR), `INST_OP_BITS'({}), `INST_MOD_BITS'({}), 1'b1, 1'b0, 1'b0, 32'b{}, 32'b{}, `FREG({}), `FREG({}), `FREG({}), `FREG({})"
name = name.format(
set_num, step, substep,
)
pc_imm = 1 if finish else 0
ucode = ucode.format(
"FINISH" if finish else "NEXT",
next_set_num, next_step, next_substep,
step,
substep,
pc_imm,
pc_imm,
rs3_rd[(step, substep)],
rs1[(set_num, substep)],
rs2[(set_num, substep)],