adding dram writeenable support + scheduler bug fixes

hw/simulate/simulator.cpp

@@ -1,5 +1,6 @@
 #include "simulator.h"
 #include <iostream>
+#include <fstream>
 #include <iomanip>
 
 uint64_t timestamp = 0;
@@ -44,6 +45,90 @@ void Simulator::attach_ram(RAM* ram) {
   dram_rsp_vec_.clear();
 }
 
+void Simulator::load_bin(const char* program_file) {
+  if (ram_ == nullptr)
+    return;
+
+  std::ifstream ifs(program_file);
+  if (!ifs) {
+    std::cout << "error: " << program_file << " not found" << std::endl;
+  }
+
+  ifs.seekg(0, ifs.end);
+  auto size = ifs.tellg();
+  std::vector<uint8_t> content(size);
+  ifs.seekg(0, ifs.beg);
+  ifs.read((char*)content.data(), size);
+
+  ram_->write(STARTUP_ADDR, size, content.data());
+}
+
+void Simulator::load_ihex(const char* program_file) {
+  if (ram_ == nullptr)
+    return;
+
+  auto hti = [&](char c)->uint32_t {
+    if (c >= 'A' && c <= 'F')
+      return c - 'A' + 10;
+    if (c >= 'a' && c <= 'f')
+      return c - 'a' + 10;
+    return c - '0';
+  };
+
+  auto hToI = [&](const char *c, uint32_t size)->uint32_t {
+    uint32_t value = 0;
+    for (uint32_t i = 0; i < size; i++) {
+      value += hti(c[i]) << ((size - i - 1) * 4);
+    }
+    return value;
+  };
+
+  std::ifstream ifs(program_file);
+  if (!ifs) {
+    std::cout << "error: " << program_file << " not found" << std::endl;
+  }
+
+  ifs.seekg(0, ifs.end);
+  uint32_t size = ifs.tellg();
+  std::vector<char> content(size);
+  ifs.seekg(0, ifs.beg);
+  ifs.read(content.data(), size);
+
+  int offset = 0;
+  char *line = content.data();
+
+  while (true) {
+    if (line[0] == ':') {
+      uint32_t byteCount = hToI(line + 1, 2);
+      uint32_t nextAddr = hToI(line + 3, 4) + offset;
+      uint32_t key = hToI(line + 7, 2);
+      switch (key) {
+      case 0:
+        for (uint32_t i = 0; i < byteCount; i++) {
+          (*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2);
+        }
+        break;
+      case 2:
+        offset = hToI(line + 9, 4) << 4;
+        break;
+      case 4:
+        offset = hToI(line + 9, 4) << 16;
+        break;
+      default:
+        break;
+      }
+    }
+    while (*line != '\n' && size != 0) {
+      ++line;
+      --size;
+    }
+    if (size <= 1)
+      break;
+    ++line;
+    --size;
+  }
+}
+
 void Simulator::print_stats(std::ostream& out) {
   out << std::left;
   out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl;
@@ -71,9 +156,7 @@ void Simulator::dbus_driver() {
   if ((dequeue_index != -1) 
    && vortex_->dram_rsp_ready) {
     vortex_->dram_rsp_valid = 1;
-    for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
-      vortex_->dram_rsp_data[i] = dram_rsp_vec_[dequeue_index].data[i];
-    }
+    memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
     vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
     free(dram_rsp_vec_[dequeue_index].data);
     dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
@@ -94,44 +177,40 @@ void Simulator::dbus_driver() {
 
   // handle DRAM requests
   if (!dram_stalled) {
-    if (vortex_->dram_req_read) {
-      dram_req_t dram_req;
-      dram_req.cycles_left = DRAM_LATENCY;     
-      dram_req.data = (unsigned*)malloc(GLOBAL_BLOCK_SIZE);
-      dram_req.tag = vortex_->dram_req_tag;
-
-      unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
-      for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
-        unsigned curr_addr = base_addr + (i * 4);
-        unsigned data_rd;
-        ram_->getWord(curr_addr, &data_rd);
-        dram_req.data[i] = data_rd;
-      }
-      dram_rsp_vec_.push_back(dram_req);
-    }
-
-    if (vortex_->dram_req_write) {
-      unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
-      for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
-        unsigned curr_addr = base_addr + (i * 4);
-        unsigned data_wr = vortex_->dram_req_data[i];
-        ram_->writeWord(curr_addr, &data_wr);
-      }
-    }
+    if (vortex_->dram_req_valid) {
+      if (vortex_->dram_req_rw) {
+        uint64_t byteen = vortex_->dram_req_byteen;
+        unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
+        uint8_t* data = (uint8_t*)(vortex_->dram_req_data);
+        for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
+          if ((byteen >> i) & 0x1) {            
+            (*ram_)[base_addr + i] = data[i];
+          }
+        }
+      } else {
+        dram_req_t dram_req;
+        dram_req.cycles_left = DRAM_LATENCY;     
+        dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
+        dram_req.tag = vortex_->dram_req_tag;
+        ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
+        dram_rsp_vec_.push_back(dram_req);
+      } 
+    }    
   }
 
   vortex_->dram_req_ready = ~dram_stalled;
 }
 
 void Simulator::io_driver() {
-  if (vortex_->io_req_write 
+  if (vortex_->io_req_valid
+   && vortex_->io_req_rw 
    && vortex_->io_req_addr == IO_BUS_ADDR_COUT) {
     uint32_t data_write = (uint32_t)vortex_->io_req_data;
     char c = (char)data_write;
     std::cout << c;      
   }
   vortex_->io_req_ready = 1;
-  vortex_->io_rsp_valid = 01;
+  vortex_->io_rsp_valid = 0;
 }
 
 void Simulator::reset() {     
@@ -251,4 +330,4 @@ bool Simulator::run() {
 #endif
 
   return (status == 1);
-}
+}