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adding dram writeenable support + scheduler bug fixes

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This commit is contained in:
Blaise Tine
2020-05-27 19:00:23 -04:00
parent a9f896b4f3
commit 9e5885b820
96 changed files with 21656 additions and 86621 deletions
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206
hw/simulate/ram.h
View File

@@ -3,24 +3,30 @@
#include <stdio.h>
#include <stdint.h>
class RAM;
uint32_t hti(char);
uint32_t hToI(const char *, uint32_t);
void loadHexImpl(const char *, RAM *);
class RAM {
private:
mutable uint8_t *mem_[(1 << 12)];
uint8_t *get(uint32_t address) const {
uint32_t block_addr = address >> 20;
uint32_t block_offset = address & 0x000FFFFF;
if (mem_[block_addr] == NULL) {
mem_[block_addr] = new uint8_t[(1 << 20)];
}
return mem_[block_addr] + block_offset;
}
public:
uint8_t *mem[1 << 12];
RAM() {
for (uint32_t i = 0; i < (1 << 12); i++)
mem[i] = NULL;
for (uint32_t i = 0; i < (1 << 12); i++) {
mem_[i] = NULL;
}
}
~RAM() {
for (uint32_t i = 0; i < (1 << 12); i++)
if (mem[i])
delete[] mem[i];
this->clear();
}
size_t size() const {
@@ -29,184 +35,30 @@ public:
void clear() {
for (uint32_t i = 0; i < (1 << 12); i++) {
if (mem[i]) {
delete mem[i];
mem[i] = NULL;
if (mem_[i]) {
delete mem_[i];
mem_[i] = NULL;
}
}
}
uint8_t *get(uint32_t address) {
if (mem[address >> 20] == NULL) {
uint8_t *ptr = new uint8_t[1024 * 1024];
for (uint32_t i = 0; i < 1024 * 1024; i += 4) {
ptr[i + 0] = 0x00;
ptr[i + 1] = 0x00;
ptr[i + 2] = 0x00;
ptr[i + 3] = 0x00;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address, uint32_t length, uint8_t *data) {
void read(uint32_t address, uint32_t length, uint8_t *data) const {
for (unsigned i = 0; i < length; i++) {
data[i] = (*this)[address + i];
data[i] = *this->get(address + i);
}
}
void write(uint32_t address, uint32_t length, uint8_t *data) {
void write(uint32_t address, uint32_t length, const uint8_t *data) {
for (unsigned i = 0; i < length; i++) {
(*this)[address + i] = data[i];
*this->get(address + i) = data[i];
}
}
void getBlock(uint32_t address, uint8_t *data) {
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t *data) {
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
}
void writeWord(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++) {
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++) {
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t &operator[](uint32_t address) {
uint8_t& operator[](uint32_t address) {
return *get(address);
}
};
// MEMORY UTILS
inline uint32_t hti(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
}
inline uint32_t hToI(const char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
const uint8_t& operator[](uint32_t address) const {
return *get(address);
}
return value;
}
inline void loadHexImpl(const char *path, RAM *mem) {
mem->clear();
FILE *fp = fopen(path, "r");
if (fp == 0) {
printf("Path not found %s\n", path);
return;
// std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t *)mem->get(0))[1] = 0xf1401073;
((uint32_t *)mem->get(0))[2] = 0x30101073;
((uint32_t *)mem->get(0))[3] = 0x800000b7;
((uint32_t *)mem->get(0))[4] = 0x000080e7;
((uint32_t *)mem->get(0x80000000))[0] = 0x00000097;
((uint32_t *)mem->get(0xb0000000))[0] = 0x01C02023;
// F00FFF10
((uint32_t *)mem->get(0xf00fff10))[0] = 0x12345678;
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char *content = new char[size];
fread(content, 1, size, fp);
int offset = 0;
char *line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI(line + 1, 2);
uint32_t nextAddr = hToI(line + 3, 4) + offset;
uint32_t key = hToI(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(mem->get(add)) = hToI(line + 9 + i * 2, 2);
}
break;
case 2:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 4;
break;
case 4:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}
if (content)
delete[] content;
}
};

139
hw/simulate/simulator.cpp
View File

@@ -1,5 +1,6 @@
#include "simulator.h"
#include <iostream>
#include <fstream>
#include <iomanip>
uint64_t timestamp = 0;
@@ -44,6 +45,90 @@ void Simulator::attach_ram(RAM* ram) {
dram_rsp_vec_.clear();
}
void Simulator::load_bin(const char* program_file) {
if (ram_ == nullptr)
return;
std::ifstream ifs(program_file);
if (!ifs) {
std::cout << "error: " << program_file << " not found" << std::endl;
}
ifs.seekg(0, ifs.end);
auto size = ifs.tellg();
std::vector<uint8_t> content(size);
ifs.seekg(0, ifs.beg);
ifs.read((char*)content.data(), size);
ram_->write(STARTUP_ADDR, size, content.data());
}
void Simulator::load_ihex(const char* program_file) {
if (ram_ == nullptr)
return;
auto hti = [&](char c)->uint32_t {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
};
auto hToI = [&](const char *c, uint32_t size)->uint32_t {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
}
return value;
};
std::ifstream ifs(program_file);
if (!ifs) {
std::cout << "error: " << program_file << " not found" << std::endl;
}
ifs.seekg(0, ifs.end);
uint32_t size = ifs.tellg();
std::vector<char> content(size);
ifs.seekg(0, ifs.beg);
ifs.read(content.data(), size);
int offset = 0;
char *line = content.data();
while (true) {
if (line[0] == ':') {
uint32_t byteCount = hToI(line + 1, 2);
uint32_t nextAddr = hToI(line + 3, 4) + offset;
uint32_t key = hToI(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
(*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2);
}
break;
case 2:
offset = hToI(line + 9, 4) << 4;
break;
case 4:
offset = hToI(line + 9, 4) << 16;
break;
default:
break;
}
}
while (*line != '\n' && size != 0) {
++line;
--size;
}
if (size <= 1)
break;
++line;
--size;
}
}
void Simulator::print_stats(std::ostream& out) {
out << std::left;
out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl;
@@ -71,9 +156,7 @@ void Simulator::dbus_driver() {
if ((dequeue_index != -1)
&& vortex_->dram_rsp_ready) {
vortex_->dram_rsp_valid = 1;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
vortex_->dram_rsp_data[i] = dram_rsp_vec_[dequeue_index].data[i];
}
memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
free(dram_rsp_vec_[dequeue_index].data);
dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
@@ -94,44 +177,40 @@ void Simulator::dbus_driver() {
// handle DRAM requests
if (!dram_stalled) {
if (vortex_->dram_req_read) {
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data = (unsigned*)malloc(GLOBAL_BLOCK_SIZE);
dram_req.tag = vortex_->dram_req_tag;
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
dram_rsp_vec_.push_back(dram_req);
}
if (vortex_->dram_req_write) {
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
if (vortex_->dram_req_valid) {
if (vortex_->dram_req_rw) {
uint64_t byteen = vortex_->dram_req_byteen;
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
uint8_t* data = (uint8_t*)(vortex_->dram_req_data);
for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
(*ram_)[base_addr + i] = data[i];
}
}
} else {
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
dram_req.tag = vortex_->dram_req_tag;
ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
dram_rsp_vec_.push_back(dram_req);
}
}
}
vortex_->dram_req_ready = ~dram_stalled;
}
void Simulator::io_driver() {
if (vortex_->io_req_write
if (vortex_->io_req_valid
&& vortex_->io_req_rw
&& vortex_->io_req_addr == IO_BUS_ADDR_COUT) {
uint32_t data_write = (uint32_t)vortex_->io_req_data;
char c = (char)data_write;
std::cout << c;
}
vortex_->io_req_ready = 1;
vortex_->io_rsp_valid = 01;
vortex_->io_rsp_valid = 0;
}
void Simulator::reset() {
@@ -251,4 +330,4 @@ bool Simulator::run() {
#endif
return (status == 1);
}
}

5
hw/simulate/simulator.h
View File

@@ -21,7 +21,7 @@
typedef struct {
int cycles_left;
unsigned *data;
uint8_t *data;
unsigned tag;
} dram_req_t;
@@ -31,6 +31,9 @@ public:
Simulator();
virtual ~Simulator();
void load_bin(const char* program_file);
void load_ihex(const char* program_file);
bool is_busy();
void reset();
void step();

39
hw/simulate/testbench.cpp
View File

@@ -58,20 +58,19 @@ int main(int argc, char **argv)
"../../benchmarks/riscv_tests/rv32um-p-remu.hex"
};
for (std::string s : tests) {
for (std::string test : tests) {
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
std::cerr << test << std::endl;
RAM ram;
loadHexImpl(s.c_str(), &ram);
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl;
std::cerr << DEFAULT;
passed = passed && curr;
}
@@ -79,37 +78,29 @@ int main(int argc, char **argv)
std::cerr << DEFAULT << "\n***************************************\n";
if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
if (!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
return !passed;
#else
char testing[] = "../../runtime/tests/simple/vx_simple_main.hex";
//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
char test[] = "../../runtime/tests/simple/vx_simple_main.hex";
//char test[] = "../../benchmarks/riscv_tests/rv32ui-p-lb.hex";
//char test[] = "../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char test[] = "../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
// const char *testing;
// if (argc >= 2) {
// testing = argv[1];
// } else {
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;
std::cerr << test << std::endl;
RAM ram;
loadHexImpl(testing, &ram);
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test);
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl;
return !curr;
return !curr;
#endif
}