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adding dram writeenable support + scheduler bug fixes

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This commit is contained in:
Blaise Tine
2020-05-27 19:00:23 -04:00
parent a9f896b4f3
commit 9e5885b820
96 changed files with 21656 additions and 86621 deletions
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195
hw/rtl/cache/VX_bank.v vendored
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@@ -18,7 +18,7 @@ module VX_bank #(
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 0,
parameter CREQ_SIZE = 0,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 0,
// Dram Fill Rsp Queue Size
@@ -56,13 +56,13 @@ module VX_bank #(
input wire reset,
// Core Request
input wire [NUM_REQUESTS-1:0] core_req_valids,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
// Core Response
output wire core_rsp_valid,
@@ -84,6 +84,7 @@ module VX_bank #(
// Dram WB Requests
output wire dram_wb_req_valid,
output wire [BANK_LINE_SIZE-1:0] dram_wb_req_byteen,
output wire [`LINE_ADDR_WIDTH-1:0] dram_wb_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_wb_req_data,
input wire dram_wb_req_ready,
@@ -99,31 +100,34 @@ module VX_bank #(
input wire snp_rsp_ready
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
wire[31:0] debug_use_pc_st0;
wire[1:0] debug_wb_st0;
wire[4:0] debug_rd_st0;
wire[`NW_BITS-1:0] debug_warp_num_st0;
wire[2:0] debug_mem_read_st0;
wire[2:0] debug_mem_write_st0;
wire debug_rw_st0;
wire[WORD_SIZE-1:0] debug_byteen_st0;
wire[`REQS_BITS-1:0] debug_tid_st0;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0;
wire[31:0] debug_use_pc_st1e;
wire[1:0] debug_wb_st1e;
wire[4:0] debug_rd_st1e;
wire[`NW_BITS-1:0] debug_warp_num_st1e;
wire[2:0] debug_mem_read_st1e;
wire[2:0] debug_mem_write_st1e;
wire debug_rw_st1e;
wire[WORD_SIZE-1:0] debug_byteen_st1e;
wire[`REQS_BITS-1:0] debug_tid_st1e;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1e;
wire[31:0] debug_use_pc_st2;
wire[1:0] debug_wb_st2;
wire[4:0] debug_rd_st2;
wire[`NW_BITS-1:0] debug_warp_num_st2;
wire[2:0] debug_mem_read_st2;
wire[2:0] debug_mem_write_st2;
wire debug_rw_st2;
wire[WORD_SIZE-1:0] debug_byteen_st2;
wire[`REQS_BITS-1:0] debug_tid_st2;
`DEBUG_END
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2;
)
wire snrq_pop;
wire snrq_empty;
@@ -177,19 +181,19 @@ module VX_bank #(
wire reqq_empty;
wire reqq_full;
wire reqq_req_st0;
wire[`REQS_BITS-1:0] reqq_req_tid_st0;
wire [`REQS_BITS-1:0] reqq_req_tid_st0;
wire reqq_req_rw_st0;
wire [WORD_SIZE-1:0] reqq_req_byteen_st0;
`IGNORE_WARNINGS_BEGIN
wire [31:0] reqq_req_addr_st0;
wire [`WORD_ADDR_WIDTH-1:0] reqq_req_addr_st0;
`IGNORE_WARNINGS_END
wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0;
VX_cache_req_queue #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.REQQ_SIZE (REQQ_SIZE),
.CREQ_SIZE (CREQ_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) req_queue (
@@ -197,28 +201,28 @@ module VX_bank #(
.reset (reset),
// Enqueue
.reqq_push (reqq_push),
.bank_valids (core_req_valids),
.bank_valids (core_req_valid),
.bank_rw (core_req_rw),
.bank_byteen (core_req_byteen),
.bank_addr (core_req_addr),
.bank_writedata (core_req_data),
.bank_tag (core_req_tag),
.bank_mem_read (core_req_read),
.bank_mem_write (core_req_write),
.bank_tag (core_req_tag),
// Dequeue
.reqq_pop (reqq_pop),
.reqq_req_st0 (reqq_req_st0),
.reqq_req_tid_st0 (reqq_req_tid_st0),
.reqq_req_rw_st0 (reqq_req_rw_st0),
.reqq_req_byteen_st0 (reqq_req_byteen_st0),
.reqq_req_addr_st0 (reqq_req_addr_st0),
.reqq_req_writedata_st0(reqq_req_writeword_st0),
.reqq_req_tag_st0 (reqq_req_tag_st0),
.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
.reqq_empty (reqq_empty),
.reqq_full (reqq_full)
);
assign core_req_ready = ~reqq_full;
assign reqq_push = (| core_req_valids) && core_req_ready;
assign reqq_push = (| core_req_valid) && core_req_ready;
wire mrvq_pop;
wire mrvq_full;
@@ -226,11 +230,11 @@ module VX_bank #(
wire mrvq_valid_st0;
wire[`REQS_BITS-1:0] mrvq_tid_st0;
wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
wire [`BASE_ADDR_BITS-1:0] mrvq_wsel_st0;
wire [`WORD_SELECT_WIDTH-1:0] mrvq_wsel_st0;
wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0;
wire [`BYTE_EN_BITS-1:0] mrvq_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] mrvq_mem_write_st0;
wire mrvq_rw_st0;
wire [WORD_SIZE-1:0] mrvq_byteen_st0;
wire mrvq_is_snp_st0;
wire mrvq_pending_hazard_st1e;
@@ -239,8 +243,8 @@ module VX_bank #(
wire[`REQS_BITS-1:0] miss_add_tid;
wire[`REQ_TAG_WIDTH-1:0] miss_add_tag;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_read;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_write;
wire miss_add_rw;
wire[WORD_SIZE-1:0] miss_add_byteen;
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
wire is_fill_st2;
@@ -268,13 +272,11 @@ module VX_bank #(
end
end
wire mrvq_pop_unqual = mrvq_valid_st0;
wire dfpq_pop_unqual = !mrvq_pop_unqual && !dfpq_empty;
wire reqq_pop_unqual = !mrvq_stop && !mrvq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && reqq_req_st0 && !is_fill_st1[0] && !is_fill_in_pipe;
wire snrq_pop_unqual = !mrvq_stop && !reqq_pop_unqual && !reqq_pop_unqual && !mrvq_pop_unqual && !dfpq_pop_unqual && !snrq_empty;
assign mrvq_pop = mrvq_pop_unqual && !stall_bank_pipe && !recover_mrvq_state_st2;
assign dfpq_pop = dfpq_pop_unqual && !stall_bank_pipe;
assign reqq_pop = reqq_pop_unqual && !stall_bank_pipe;
@@ -283,7 +285,7 @@ module VX_bank #(
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
wire [`WORD_SELECT_ADDR_END:0] qual_wsel_st0;
wire [`WORD_SELECT_WIDTH-1:0] qual_wsel_st0;
wire qual_from_mrvq_st0;
wire [`WORD_WIDTH-1:0] qual_writeword_st0;
@@ -294,7 +296,7 @@ module VX_bank #(
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_WIDTH-1:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0];
@@ -307,24 +309,24 @@ module VX_bank #(
assign qual_addr_st0 = dfpq_pop_unqual ? dfpq_addr_st0 :
mrvq_pop_unqual ? mrvq_addr_st0 :
reqq_pop_unqual ? reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] :
reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] :
snrq_pop_unqual ? snrq_addr_st0 :
0;
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`BASE_ADDR_BITS-1:0] :
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 :
0;
assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), `BYTE_EN_BITS'(0), `BYTE_EN_BITS'(0), `REQS_BITS'(0)} :
assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} :
reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} :
snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} :
0;
assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 :
(mrvq_pop_unqual && (mrvq_mem_write_st0 != `BYTE_EN_NO)) ? 1 :
(reqq_pop_unqual && (reqq_req_mem_write_st0 != `BYTE_EN_NO)) ? 1 :
(mrvq_pop_unqual && mrvq_rw_st0) ? 1 :
(reqq_pop_unqual && reqq_req_rw_st0) ? 1 :
0;
assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 :
@@ -337,14 +339,14 @@ module VX_bank #(
assign qual_from_mrvq_st0 = mrvq_pop_unqual;
`DEBUG_BEGIN
`DEBUG_BLOCK(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0;
assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = qual_inst_meta_st0;
end
`DEBUG_END
)
VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_c0 (
.clk (clk),
.reset (reset),
@@ -357,7 +359,7 @@ module VX_bank #(
genvar i;
for (i = 1; i < STAGE_1_CYCLES; i++) begin
VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_cc (
.clk (clk),
.reset(reset),
@@ -369,16 +371,17 @@ module VX_bank #(
end
wire[`WORD_WIDTH-1:0] readword_st1e;
wire[`BANK_LINE_WIDTH-1:0] readdata_st1e;
wire[`BANK_LINE_WIDTH-1:0] readdata_st1e;
wire[`TAG_SELECT_BITS-1:0] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
wire[BANK_LINE_SIZE-1:0] dirtyb_st1e;
`DEBUG_BEGIN
wire [`REQ_TAG_WIDTH-1:0] tag_st1e;
wire [`REQS_BITS-1:0] tid_st1e;
`DEBUG_END
wire [`BYTE_EN_BITS-1:0] mem_read_st1e;
wire [`BYTE_EN_BITS-1:0] mem_write_st1e;
wire mem_rw_st1e;
wire [WORD_SIZE-1:0] mem_byteen_st1e;
wire fill_saw_dirty_st1e;
wire is_snp_st1e;
wire snp_to_mrvq_st1e;
@@ -392,12 +395,11 @@ module VX_bank #(
assign valid_st1e = valid_st1 [STAGE_1_CYCLES-1];
assign is_snp_st1e = is_snp_st1 [STAGE_1_CYCLES-1];
assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign {tag_st1e, mem_rw_st1e, mem_byteen_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign st2_pending_hazard_st1e = (miss_add_because_miss) && ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e)) || (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e)) || (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign mrvq_recover_ready_state_st1e = valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2 && (addr_st2 == addr_st1[STAGE_1_CYCLES-1]);
@@ -421,17 +423,17 @@ module VX_bank #(
.readaddr_st10(addr_st1[0][`LINE_SELECT_BITS-1:0]),
// Actual Read/Write
.valid_req_st1e(valid_st1e),
.writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e(wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]),
.valid_req_st1e (valid_st1e),
.writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e (wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e),
.mem_read_st1e (mem_read_st1e),
.mem_rw_st1e (mem_rw_st1e),
.mem_byteen_st1e (mem_byteen_st1e),
.is_snp_st1e (is_snp_st1e),
.is_snp_st1e (is_snp_st1e),
// Read Data
.readword_st1e (readword_st1e),
@@ -439,27 +441,28 @@ module VX_bank #(
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e),
.dirtyb_st1e (dirtyb_st1e),
.fill_saw_dirty_st1e (fill_saw_dirty_st1e),
.snp_to_mrvq_st1e (snp_to_mrvq_st1e),
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_tagid_st1e, debug_rw_st1e, debug_byteen_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
end
`DEBUG_END
)
wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1];
wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e;
wire valid_st2;
wire [`BASE_ADDR_BITS-1:0] wsel_st2;
wire [`WORD_SELECT_WIDTH-1:0] wsel_st2;
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2;
wire [`BANK_LINE_WIDTH-1:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire [BANK_LINE_SIZE-1:0] dirtyb_st2;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2;
wire [`TAG_SELECT_BITS-1:0] readtag_st2;
wire fill_saw_dirty_st2;
@@ -474,22 +477,21 @@ module VX_bank #(
wire recover_mrvq_state_st2;
VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH)
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(1'b0),
.in ({mrvq_recover_ready_state_st1e, from_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_recover_ready_state_st2 , from_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
.in ({mrvq_recover_ready_state_st1e, from_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, dirtyb_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_recover_ready_state_st2 , from_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , dirtyb_st2, inst_meta_st2 })
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2;
assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2;
end
`DEBUG_END
)
// Enqueue to miss reserv if it's a valid miss
assign miss_add_because_miss = valid_st2 && !is_snp_st2 && miss_st2;
@@ -509,14 +511,13 @@ module VX_bank #(
assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2;
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`BASE_ADDR_BITS-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_SELECT_WIDTH-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2;
assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2;
wire miss_add_is_snp = is_snp_st2;
wire miss_add_from_mrvq = valid_st2 && from_mrvq_st2 && !stall_bank_pipe;
assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == qual_addr_st0 );
assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1[STAGE_1_CYCLES-1]);
@@ -544,8 +545,8 @@ module VX_bank #(
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_tag (miss_add_tag),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_add_rw (miss_add_rw),
.miss_add_byteen (miss_add_byteen),
.miss_add_is_snp (miss_add_is_snp),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
@@ -564,8 +565,8 @@ module VX_bank #(
.miss_resrv_data_st0 (mrvq_writeword_st0),
.miss_resrv_tid_st0 (mrvq_tid_st0),
.miss_resrv_tag_st0 (mrvq_tag_st0),
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
.miss_resrv_mem_write_st0(mrvq_mem_write_st0),
.miss_resrv_rw_st0 (mrvq_rw_st0),
.miss_resrv_byteen_st0 (mrvq_byteen_st0),
.miss_resrv_is_snp_st0 (mrvq_is_snp_st0)
);
@@ -581,10 +582,12 @@ module VX_bank #(
assign cwbq_push = cwbq_push_unqual
&& !cwbq_full
&& (miss_add_mem_write == `BYTE_EN_NO)
&& (miss_add_rw == 0)
&& !(dwbq_push_stall
|| mrvq_push_stall
|| dram_fill_req_stall);
|| dram_fill_req_stall);
assign cwbq_pop = core_rsp_valid && core_rsp_ready;
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid;
@@ -605,10 +608,9 @@ module VX_bank #(
.empty (cwbq_empty),
.full (cwbq_full),
`UNUSED_PIN (size)
);
);
assign core_rsp_valid = !cwbq_empty;
assign cwbq_pop = core_rsp_valid && core_rsp_ready;
// Enqueue DRAM fill request
@@ -664,23 +666,22 @@ module VX_bank #(
|| mrvq_push_stall
|| dram_fill_req_stall);
wire [`BANK_LINE_WIDTH-1:0] dwbq_req_data = readdata_st2;
wire [`LINE_ADDR_WIDTH-1:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st2 = SNP_REQ_TAG_WIDTH'(miss_add_tag);
VX_generic_queue #(
.DATAW(1 + 1 + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH),
.DATAW(1 + 1 + BANK_LINE_SIZE + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH),
.SIZE(DWBQ_SIZE)
) dwb_queue (
.clk (clk),
.reset (reset),
.push (dwbq_push),
.data_in ({dwbq_is_dwb_in, dwbq_is_snp_in, dwbq_req_addr, dwbq_req_data, snrq_tag_st2}),
.data_in ({dwbq_is_dwb_in, dwbq_is_snp_in, dirtyb_st2, dwbq_req_addr, readdata_st2, snrq_tag_st2}),
.pop (dwbq_pop),
.data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
.data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_byteen, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
.empty (dwbq_empty),
.full (dwbq_full),
`UNUSED_PIN (size)
@@ -717,25 +718,25 @@ module VX_bank #(
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, dram_fill_req_addr);
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, dram_wb_req_addr, dram_wb_req_data);
$display("%t: bank%01d%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_wb_req_addr), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, dram_fill_rsp_addr, dram_fill_rsp_data);
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end
end
end else begin
always_ff @(posedge clk) begin
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
$display("%t: bank%01d%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end
end

81
hw/rtl/cache/VX_cache.v vendored
View File

@@ -18,7 +18,7 @@ module VX_cache #(
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
parameter CREQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 16,
// Dram Fill Rsp Queue Size
@@ -69,23 +69,24 @@ module VX_cache #(
input wire reset,
// Core request
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
output wire core_req_ready,
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready,
input wire core_rsp_ready,
// DRAM request
output wire dram_req_read,
output wire dram_req_write,
output wire dram_req_valid,
output wire dram_req_rw,
output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
@@ -122,22 +123,18 @@ module VX_cache #(
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb;
wire[2:0] debug_core_req_rmask;
wire[4:0] debug_core_req_rd;
wire[`NW_BITS-1:0] debug_core_req_warp_num;
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rmask, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
end
`DEBUG_END
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;
)
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;
wire [NUM_BANKS-1:0] per_bank_core_req_ready;
@@ -155,6 +152,7 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_dram_wb_req_ready;
wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_wb_req_byteen;
wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr;
wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data;
@@ -226,18 +224,18 @@ module VX_cache #(
) cache_core_req_bank_sel (
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids (per_bank_valids)
.per_bank_valid (per_bank_valid)
);
genvar i;
generate
for (i = 0; i < NUM_BANKS; i++) begin
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_write;
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid;
wire [NUM_REQUESTS-1:0] curr_bank_core_req_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
wire curr_bank_core_rsp_valid;
wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid;
@@ -250,11 +248,12 @@ module VX_cache #(
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr;
wire curr_bank_dram_fill_rsp_ready;
wire curr_bank_dram_fill_req_valid;
wire curr_bank_dram_fill_req_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_fill_req_ready;
wire curr_bank_dram_wb_req_valid;
wire [BANK_LINE_SIZE-1:0] curr_bank_dram_wb_req_byteen;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_dram_wb_req_ready;
@@ -271,12 +270,12 @@ module VX_cache #(
wire curr_bank_core_req_ready;
// Core Req
assign curr_bank_core_req_valids = per_bank_valids[i] & {NUM_REQUESTS{core_req_ready}};
assign curr_bank_core_req_valid = per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}};
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_rw = core_req_rw;
assign curr_bank_core_req_byteen = core_req_byteen;
assign curr_bank_core_req_data = core_req_data;
assign curr_bank_core_req_tag = core_req_tag;
assign curr_bank_core_req_read = core_req_read;
assign curr_bank_core_req_write = core_req_write;
assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
// Core WB
@@ -308,10 +307,11 @@ module VX_cache #(
// Dram writeback request
assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid;
assign per_bank_dram_wb_req_byteen[i] = curr_bank_dram_wb_req_byteen;
if (NUM_BANKS == 1) begin
assign per_bank_dram_wb_req_addr[i] = curr_bank_dram_wb_req_addr;
end else begin
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
end
assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data;
assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i];
@@ -341,7 +341,7 @@ module VX_cache #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.CREQ_SIZE (CREQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
@@ -358,9 +358,9 @@ module VX_cache #(
.clk (clk),
.reset (reset),
// Core request
.core_req_valids (curr_bank_core_req_valids),
.core_req_read (curr_bank_core_req_read),
.core_req_write (curr_bank_core_req_write),
.core_req_valid (curr_bank_core_req_valid),
.core_req_rw (curr_bank_core_req_rw),
.core_req_byteen (curr_bank_core_req_byteen),
.core_req_addr (curr_bank_core_req_addr),
.core_req_data (curr_bank_core_req_data),
.core_req_tag (curr_bank_core_req_tag),
@@ -386,6 +386,7 @@ module VX_cache #(
// Dram writeback request
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
.dram_wb_req_byteen (curr_bank_dram_wb_req_byteen),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data),
.dram_wb_req_ready (curr_bank_dram_wb_req_ready),
@@ -418,11 +419,13 @@ module VX_cache #(
.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
.dram_fill_req_ready (dram_fill_req_ready),
.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
.per_bank_dram_wb_req_byteen (per_bank_dram_wb_req_byteen),
.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
.per_bank_dram_wb_req_ready (per_bank_dram_wb_req_ready),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_ready (dram_req_ready)

25
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -5,11 +5,11 @@
`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_REQ_TAG_WIDTH)
// data tid tag read write base addr is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS + 1)
// tag rw byteen tid
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// tag read write reqs
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS)
// data metadata word_sel is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `WORD_SELECT_WIDTH + 1)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)
@@ -27,36 +27,39 @@
`define OFFSET_ADDR_BITS `CLOG2(WORD_SIZE)
`define OFFSET_ADDR_START 0
`define OFFSET_ADDR_END (`OFFSET_ADDR_START+`OFFSET_ADDR_BITS-1)
`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
// Word select
`define WORD_SELECT_BITS `CLOG2(`BANK_LINE_WORDS)
`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
`define WORD_SELECT_ADDR_END (`WORD_SELECT_ADDR_START+`WORD_SELECT_BITS-1)
`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
// Bank select
`define BANK_SELECT_BITS `CLOG2(NUM_BANKS)
`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
`define BANK_SELECT_ADDR_END (`BANK_SELECT_ADDR_START+`BANK_SELECT_BITS-1)
`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
// Line select
`define LINE_SELECT_BITS `CLOG2(`BANK_LINE_COUNT)
`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
`define LINE_SELECT_ADDR_END (`LINE_SELECT_ADDR_START+`LINE_SELECT_BITS-1)
`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
// Tag select
`define TAG_SELECT_BITS (31-`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_END 31
`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START
`define WORD_SELECT_WIDTH `LOG2UP(`BANK_LINE_WORDS)
`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))
`define DRAM_ADDR_WIDTH (32-`CLOG2(BANK_LINE_SIZE))
`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS)
`define BANK_SELECT_ADDR_RNG (`BANK_SELECT_BITS+`WORD_SELECT_BITS-1):`WORD_SELECT_BITS
`define LINE_SELECT_ADDR_RNG `WORD_ADDR_WIDTH-1:(`BANK_SELECT_BITS + `WORD_SELECT_BITS)
`define TAG_LINE_ADDR_RNG `LINE_ADDR_WIDTH-1:`LINE_SELECT_BITS
`define BASE_ADDR_BITS (`WORD_SELECT_BITS+`OFFSET_ADDR_BITS)
@@ -69,8 +72,12 @@
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
`define BYTE_TO_WORD_ADDR(x, w) (32-`CLOG2(w))'(x >> `CLOG2(w))
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, `BANK_SELECT_BITS'(i), `BASE_ADDR_BITS'(0)}
`define LINE_TO_BYTE_ADDR0(x) {x, `BASE_ADDR_BITS'(0)}
`endif

12
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -13,24 +13,24 @@ module VX_cache_core_req_bank_sel #(
) (
input wire [NUM_REQUESTS-1:0] core_req_valid,
`IGNORE_WARNINGS_BEGIN
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
`IGNORE_WARNINGS_END
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid
);
integer i;
if (NUM_BANKS == 1) begin
always @(*) begin
per_bank_valids = 0;
per_bank_valid = 0;
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valids[0][i] = core_req_valid[i];
per_bank_valid[0][i] = core_req_valid[i];
end
end
end else begin
always @(*) begin
per_bank_valids = 0;
per_bank_valid = 0;
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valids[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
per_bank_valid[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
end
end
end

15
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -31,14 +31,13 @@ module VX_cache_core_rsp_merge #(
assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
wire [`BANK_BITS-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) sel_bank (
.valids(per_bank_core_rsp_valid),
.index (main_bank_index),
.found (found_bank)
`UNUSED_PIN (found)
);
integer i;
@@ -47,13 +46,8 @@ module VX_cache_core_rsp_merge #(
assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index];
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (found_bank
&& per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))
if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
@@ -66,11 +60,8 @@ module VX_cache_core_rsp_merge #(
end else begin
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (found_bank
&& per_bank_core_rsp_valid[i]
if (per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin

15
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View File

@@ -23,13 +23,15 @@ module VX_cache_dram_req_arb #(
// Writeback Request
input wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid,
input wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_wb_req_byteen,
input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr,
input wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data,
output wire [NUM_BANKS-1:0] per_bank_dram_wb_req_ready,
// Merged Request
output wire dram_req_read,
output wire dram_req_write,
output wire dram_req_valid,
output wire dram_req_rw,
output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
@@ -54,7 +56,7 @@ module VX_cache_dram_req_arb #(
.clk (clk),
.reset (reset),
.dram_req (dram_req_read),
.dram_req (dram_req_valid && ~dram_req_rw),
.dram_req_addr(dram_req_addr),
.pref_pop (pref_pop),
@@ -106,10 +108,9 @@ module VX_cache_dram_req_arb #(
assign per_bank_dram_wb_req_ready[i] = dram_req_ready && (dwb_bank == `BANK_BITS'(i));
end
wire dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid;
assign dram_req_write = dwb_valid && dram_req_valid;
assign dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_rw = dwb_valid;
assign dram_req_byteen = dwb_valid ? per_bank_dram_wb_req_byteen[dwb_bank] : {BANK_LINE_SIZE{1'b1}};
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
assign {dram_req_data} = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;

16
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -25,12 +25,12 @@ module VX_cache_miss_resrv #(
input wire miss_add,
input wire from_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel,
input wire[`WORD_SELECT_WIDTH-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write,
input wire miss_add_rw,
input wire[WORD_SIZE-1:0] miss_add_byteen,
input wire mrvq_init_ready_state,
input wire miss_add_is_snp,
output wire miss_resrv_full,
@@ -46,12 +46,12 @@ module VX_cache_miss_resrv #(
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0,
output wire[`WORD_SELECT_WIDTH-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0,
output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0,
output wire miss_resrv_rw_st0,
output wire[WORD_SIZE-1:0] miss_resrv_byteen_st0,
output wire miss_resrv_is_snp_st0
);
reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0];
@@ -93,7 +93,7 @@ module VX_cache_miss_resrv #(
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_rw_st0, miss_resrv_byteen_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && !from_mrvq && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
@@ -124,7 +124,7 @@ module VX_cache_miss_resrv #(
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= mrvq_init_ready_state;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel, miss_add_is_snp};
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_wsel, miss_add_is_snp};
tail_ptr <= tail_ptr + 1;
end else if (increment_head) begin
valid_table[head_ptr] <= 0;

90
hw/rtl/cache/VX_cache_req_queue.v vendored
View File

@@ -6,7 +6,7 @@ module VX_cache_req_queue #(
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 0,
// Core Request Queue Size
parameter REQQ_SIZE = 0,
parameter CREQ_SIZE = 0,
// core request tag size
parameter CORE_TAG_WIDTH = 0,
// size of tag id in core request tag
@@ -16,22 +16,22 @@ module VX_cache_req_queue #(
input wire reset,
// Enqueue Data
input wire reqq_push,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] bank_mem_read,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] bank_mem_write,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] bank_writedata,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] bank_tag,
input wire reqq_push,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0] bank_rw,
input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] bank_byteen,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] bank_writedata,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] bank_addr,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] bank_tag,
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`REQS_BITS-1:0] reqq_req_tid_st0,
output wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0,
output wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0,
output wire reqq_req_rw_st0,
output wire [WORD_SIZE-1:0] reqq_req_byteen_st0,
output wire [`WORD_ADDR_WIDTH-1:0] reqq_req_addr_st0,
output wire [`WORD_WIDTH-1:0] reqq_req_writedata_st0,
output wire [31:0] reqq_req_addr_st0,
output wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0,
// State Data
@@ -39,30 +39,26 @@ module VX_cache_req_queue #(
output wire reqq_full
);
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0][31:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] out_per_writedata;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] out_per_mem_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] out_per_mem_write;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] out_per_tag;
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0] out_per_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] out_per_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] out_per_writedata;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] out_per_tag;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0][31:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] use_per_writedata;
reg [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] use_per_mem_read;
reg [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] use_per_mem_write;
reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] use_per_tag;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0] use_per_rw;
reg [NUM_REQUESTS-1:0][WORD_SIZE-1:0] use_per_byteen;
reg [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] use_per_writedata;
reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] use_per_tag;
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0][31:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] qual_writedata;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] qual_mem_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] qual_mem_write;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] qual_tag;
`DEBUG_BEGIN
reg [NUM_REQUESTS-1:0] updated_valids;
`DEBUG_END
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0] qual_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] qual_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] qual_writedata;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] qual_tag;
wire o_empty;
@@ -73,15 +69,15 @@ module VX_cache_req_queue #(
wire pop_qual = !out_empty && use_empty;
VX_generic_queue #(
.DATAW($bits(bank_valids) + $bits(bank_addr) + $bits(bank_writedata) + $bits(bank_tag) + $bits(bank_mem_read) + $bits(bank_mem_write)),
.SIZE(REQQ_SIZE)
.DATAW($bits(bank_valids) + $bits(bank_addr) + $bits(bank_writedata) + $bits(bank_tag) + $bits(bank_rw) + $bits(bank_byteen)),
.SIZE(CREQ_SIZE)
) reqq_queue (
.clk (clk),
.reset (reset),
.push (push_qual),
.data_in ({bank_valids, bank_addr, bank_writedata, bank_tag, bank_mem_read, bank_mem_write}),
.data_in ({bank_valids, bank_rw, bank_byteen, bank_addr, bank_writedata, bank_tag}),
.pop (pop_qual),
.data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
.data_out ({out_per_valids, out_per_rw, out_per_byteen, out_per_addr, out_per_writedata, out_per_tag}),
.empty (o_empty),
.full (reqq_full),
`UNUSED_PIN (size)
@@ -93,8 +89,8 @@ module VX_cache_req_queue #(
assign qual_addr = use_per_addr;
assign qual_writedata = use_per_writedata;
assign qual_tag = use_per_tag;
assign qual_mem_read = use_per_mem_read;
assign qual_mem_write = use_per_mem_write;
assign qual_rw = use_per_rw;
assign qual_byteen = use_per_byteen;
wire[`REQS_BITS-1:0] qual_request_index;
wire qual_has_request;
@@ -110,6 +106,8 @@ module VX_cache_req_queue #(
assign reqq_empty = !qual_has_request;
assign reqq_req_st0 = qual_has_request;
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_rw_st0 = qual_rw[qual_request_index];
assign reqq_req_byteen_st0 = qual_byteen[qual_request_index];
assign reqq_req_addr_st0 = qual_addr[qual_request_index];
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
@@ -117,17 +115,17 @@ module VX_cache_req_queue #(
assign reqq_req_tag_st0 = qual_tag;
end else begin
assign reqq_req_tag_st0 = qual_tag[qual_request_index];
end
assign reqq_req_mem_read_st0 = qual_mem_read [qual_request_index];
assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index];
end
`DEBUG_BLOCK(
reg [NUM_REQUESTS-1:0] updated_valids;
always @(*) begin
updated_valids = qual_valids;
if (qual_has_request) begin
updated_valids[qual_request_index] = 0;
end
end
)
always @(posedge clk) begin
if (reset) begin
@@ -135,11 +133,11 @@ module VX_cache_req_queue #(
end else begin
if (pop_qual) begin
use_per_valids <= real_out_per_valids;
use_per_rw <= out_per_rw;
use_per_byteen <= out_per_byteen;
use_per_addr <= out_per_addr;
use_per_writedata <= out_per_writedata;
use_per_tag <= out_per_tag;
use_per_mem_read <= out_per_mem_read;
use_per_mem_write <= out_per_mem_write;
use_per_tag <= out_per_tag;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= 0;
end

126
hw/rtl/cache/VX_tag_data_access.v vendored
View File

@@ -35,10 +35,10 @@ module VX_tag_data_access #(
input wire[`WORD_WIDTH-1:0] writeword_st1e,
input wire[`BANK_LINE_WIDTH-1:0] writedata_st1e,
`IGNORE_WARNINGS_BEGIN
input wire[`WORD_SELECT_ADDR_END:0] writewsel_st1e,
input wire[`BYTE_EN_BITS-1:0] mem_write_st1e,
input wire[`BYTE_EN_BITS-1:0] mem_read_st1e,
`IGNORE_WARNINGS_BEGIN
input wire mem_rw_st1e,
input wire[WORD_SIZE-1:0] mem_byteen_st1e,
input wire[`WORD_SELECT_WIDTH-1:0] writewsel_st1e,
`IGNORE_WARNINGS_END
output wire[`WORD_WIDTH-1:0] readword_st1e,
@@ -46,6 +46,7 @@ module VX_tag_data_access #(
output wire[`TAG_SELECT_BITS-1:0] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e,
output wire[BANK_LINE_SIZE-1:0] dirtyb_st1e,
output wire fill_saw_dirty_st1e,
output wire snp_to_mrvq_st1e,
output wire mrvq_init_ready_state_st1e
@@ -53,16 +54,19 @@ module VX_tag_data_access #(
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[BANK_LINE_SIZE-1:0] read_dirtyb_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`BANK_LINE_WIDTH-1:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[BANK_LINE_SIZE-1:0] qual_read_dirtyb_st1;
wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1;
wire[`BANK_LINE_WIDTH-1:0] qual_read_data_st1;
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_st1e;
wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e;
wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e;
wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_write_enable;
@@ -90,8 +94,9 @@ module VX_tag_data_access #(
.stall_bank_pipe(stall_bank_pipe),
.read_addr (readaddr_st10),
.read_valid (qual_read_valid_st1),
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_dirtyb (qual_read_dirtyb_st1),
.read_tag (qual_read_tag_st1),
.read_data (qual_read_data_st1),
@@ -105,126 +110,56 @@ module VX_tag_data_access #(
);
VX_generic_register #(
.N(1 + 1 + `TAG_SELECT_BITS + `BANK_LINE_WIDTH),
.N(1 + 1 + BANK_LINE_SIZE + `TAG_SELECT_BITS + `BANK_LINE_WIDTH),
.PassThru(1)
) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(1'b0),
.in({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}),
.out({read_valid_st1c[0], read_dirty_st1c[0], read_tag_st1c[0], read_data_st1c[0]})
.in({qual_read_valid_st1, qual_read_dirty_st1, qual_read_dirtyb_st1, qual_read_tag_st1, qual_read_data_st1}),
.out({read_valid_st1c[0], read_dirty_st1c[0], read_dirtyb_st1c[0], read_tag_st1c[0], read_data_st1c[0]})
);
genvar i;
for (i = 1; i < STAGE_1_CYCLES-1; i++) begin
VX_generic_register #(
.N( 1 + 1 + `TAG_SELECT_BITS + `BANK_LINE_WIDTH)
.N( 1 + 1 + BANK_LINE_SIZE + `TAG_SELECT_BITS + `BANK_LINE_WIDTH)
) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(1'b0),
.in({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}),
.out({read_valid_st1c[i], read_dirty_st1c[i], read_tag_st1c[i], read_data_st1c[i]})
.in({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_dirtyb_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}),
.out({read_valid_st1c[i], read_dirty_st1c[i], read_dirtyb_st1c[i], read_tag_st1c[i], read_data_st1c[i]})
);
end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM
assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1];
assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1];
wire force_write = real_writefill;
wire should_write;
assign readword_st1e = use_read_data_st1e[writewsel_st1e * `WORD_WIDTH +: `WORD_WIDTH];
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we;
wire [`BANK_LINE_WIDTH-1:0] data_write;
if (WORD_SIZE == BANK_LINE_SIZE) begin
wire should_write = mem_rw_st1e
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
assign should_write = ((mem_write_st1e != `BYTE_EN_NO))
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write = (writewsel_st1e == `WORD_SELECT_WIDTH'(i)) && should_write && !real_writefill;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
assign we[i] = (force_write || (should_write && !real_writefill)) ? {WORD_SIZE{1'b1}} : {WORD_SIZE{1'b0}};
end
assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} :
normal_write ? mem_byteen_st1e:
{WORD_SIZE{1'b0}};
assign readword_st1e = use_read_data_st1e;
assign data_write = force_write ? writedata_st1e : writeword_st1e;
end else begin
wire[`OFFSET_ADDR_BITS-1:0] byte_select = writewsel_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_BITS-1:0] block_offset = writewsel_st1e[`WORD_SELECT_ADDR_RNG];
wire lb = valid_req_st1e && (mem_read_st1e == `BYTE_EN_LB);
wire lh = valid_req_st1e && (mem_read_st1e == `BYTE_EN_LH);
wire lbu = valid_req_st1e && (mem_read_st1e == `BYTE_EN_HB);
wire lhu = valid_req_st1e && (mem_read_st1e == `BYTE_EN_HH);
wire lw = valid_req_st1e && (mem_read_st1e == `BYTE_EN_LW);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire sb = valid_req_st1e && (mem_write_st1e == `BYTE_EN_LB);
wire sh = valid_req_st1e && (mem_write_st1e == `BYTE_EN_LH);
wire sw = valid_req_st1e && (mem_write_st1e == `BYTE_EN_LW);
wire [3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire [3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
assign should_write = (sw || sb || sh)
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
wire[`WORD_WIDTH-1:0] data_unmod = use_read_data_st1e[block_offset * 32 +: 32];
wire[`WORD_WIDTH-1:0] data_unQual = (b0 || lw) ? (data_unmod) :
b1 ? (data_unmod >> 8) :
b2 ? (data_unmod >> 16) :
(data_unmod >> 24);
wire[`WORD_WIDTH-1:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[`WORD_WIDTH-1:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[`WORD_WIDTH-1:0] lbu_data = (data_unQual & 32'hFF);
wire[`WORD_WIDTH-1:0] lhu_data = (data_unQual & 32'hFFFF);
wire[`WORD_WIDTH-1:0] lw_data = (data_unQual);
wire[`WORD_WIDTH-1:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readword_st1e = data_Qual;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write = (block_offset == `WORD_SELECT_BITS'(i)) && should_write && !real_writefill;
assign we[i] = (force_write) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
wire [`WORD_WIDTH-1:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} :
writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] sw_data = writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] use_write_dat = sb ? sb_data : sh ? sh_data : sw_data;
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = force_write ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : use_write_dat;
end
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e;
end
assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we;
@@ -242,7 +177,7 @@ module VX_tag_data_access #(
wire force_core_miss = (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e && !real_miss);
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
// The second term is basically saying always make an entry ready if there's already antoher entry waiting, even if you yourself see a miss
assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e || (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e);
@@ -250,6 +185,7 @@ module VX_tag_data_access #(
assign miss_st1e = real_miss || snoop_hit_no_pending || force_core_miss;
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;
assign dirtyb_st1e = use_read_dirtyb_st1e;
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;
assign fill_sent = miss_st1e;

40
hw/rtl/cache/VX_tag_data_structure.v vendored
View File

@@ -17,6 +17,7 @@ module VX_tag_data_structure #(
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire read_valid,
output wire read_dirty,
output wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] read_dirtyb,
output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire[`BANK_LINE_WIDTH-1:0] read_data,
@@ -30,35 +31,41 @@ module VX_tag_data_structure #(
);
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg valid [`BANK_LINE_COUNT-1:0];
reg dirty [`BANK_LINE_COUNT-1:0];
assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr];
assign read_tag = tag [read_addr];
assign read_data = data [read_addr];
assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr];
assign read_dirtyb = dirtyb [read_addr];
assign read_tag = tag [read_addr];
assign read_data = data [read_addr];
wire going_to_write = (| write_enable);
wire do_write = (| write_enable);
integer i;
integer i, j;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < `BANK_LINE_COUNT; i++) begin
valid[i] <= 0;
dirty[i] <= 0;
valid[i] <= 0;
dirty[i] <= 0;
dirtyb[i] <= 0;
end
end else if (!stall_bank_pipe) begin
if (going_to_write) begin
if (do_write) begin
valid[write_addr] <= 1;
tag [write_addr] <= tag_index;
if (write_fill) begin
dirty[write_addr] <= 0;
dirty[write_addr] <= 0;
dirtyb[write_addr] <= 0;
end else begin
dirty[write_addr] <= 1;
dirty[write_addr] <= 1;
dirtyb[write_addr] <= dirtyb[write_addr] | write_enable;
end
end else if (fill_sent) begin
dirty[write_addr] <= 0;
dirty[write_addr] <= 0;
dirtyb[write_addr] <= 0;
end
if (invalidate) begin
@@ -66,10 +73,11 @@ module VX_tag_data_structure #(
end
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * 8 +: 8];
if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * 8 +: 8];
if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * 8 +: 8];
if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * 8 +: 8];
for (j = 0; j < WORD_SIZE; j++) begin
if (write_enable[i][j]) begin
data[write_addr][i][j] <= write_data[i * `WORD_WIDTH + j * 8 +: 8];
end
end
end
end
end