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adding dram writeenable support + scheduler bug fixes

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This commit is contained in:
Blaise Tine
2020-05-27 19:00:23 -04:00
parent a9f896b4f3
commit 9e5885b820
96 changed files with 21656 additions and 86621 deletions
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1
hw/.gitignore vendored Normal file
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@@ -0,0 +1 @@
obj_dir/*

6
hw/Makefile
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@@ -25,7 +25,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-DDBG_PRINT_DRAM \
-DDBG_PRINT_OPAE
#DBG_PRINT=$(DBG_PRINT_FLAGSs)
DBG_PRINT=$(DBG_PRINT_FLAGS)
INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate
@@ -44,7 +44,7 @@ gen-s: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG'
gen-sd: build_config
verilator $(VF) -cc Vortex_Socket.v $(DBG_PRINT) -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG)
verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG)
gen-st: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
@@ -53,7 +53,7 @@ gen-m: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
gen-md: build_config
verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) $(DBG_PRINT) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
gen-mt: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)

2
hw/opae/vortex_afu.sv
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@@ -737,7 +737,7 @@ Vortex_Socket #() vx_socket (
// I/O response
.io_rsp_valid (1'b0),
.io_rsp_data (32'b0),
.io_rsp_tag (`CORE_REQ_TAG_WIDTH'(0)),
.io_rsp_tag (`DCORE_TAG_WIDTH'(0)),
.io_rsp_ready (),
// status

14
hw/rtl/VX_back_end.v
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@@ -25,14 +25,6 @@ module VX_back_end #(
output wire ebreak
);
VX_wb_if wb_temp_if();
assign writeback_if.wb = wb_temp_if.wb;
assign writeback_if.rd = wb_temp_if.rd;
assign writeback_if.data = wb_temp_if.data;
assign writeback_if.valid = wb_temp_if.valid;
assign writeback_if.warp_num = wb_temp_if.warp_num;
assign writeback_if.pc = wb_temp_if.pc;
wire no_slot_mem;
wire no_slot_exec;
@@ -57,7 +49,7 @@ module VX_back_end #(
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.writeback_if (wb_temp_if),
.writeback_if (writeback_if),
.bckE_req_if (bckE_req_if),
// New
.exec_unit_req_if (exec_unit_req_if),
@@ -109,7 +101,7 @@ module VX_back_end #(
.reset (reset),
.no_slot_csr (no_slot_csr),
.csr_req_if (csr_req_if),
.writeback_if (wb_temp_if),
.writeback_if (writeback_if),
.csr_wb_if (csr_wb_if),
.stall_gpr_csr (stall_gpr_csr)
);
@@ -121,7 +113,7 @@ module VX_back_end #(
.inst_exec_wb_if(inst_exec_wb_if),
.csr_wb_if (csr_wb_if),
.writeback_if (wb_temp_if),
.writeback_if (writeback_if),
.no_slot_mem (no_slot_mem),
.no_slot_exec (no_slot_exec),
.no_slot_csr (no_slot_csr)

81
hw/rtl/VX_config.vh
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@@ -28,15 +28,15 @@
`endif
`ifndef NUM_CSRS
`define NUM_CSRS 2
`define NUM_CSRS 1024
`endif
`ifndef STARTUP_ADDR
`define STARTUP_ADDR 32'h80000000
`endif
`ifndef SHARED_MEM_TOP_ADDR
`define SHARED_MEM_TOP_ADDR 8'hFE
`ifndef SHARED_MEM_BASE_ADDR
`define SHARED_MEM_BASE_ADDR 32'hFE000000
`endif
`ifndef STACK_BASE_ADDR
@@ -48,7 +48,7 @@
`endif
`ifndef IO_BUS_ADDR_COUT
`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
`define IO_BUS_ADDR_COUT 30'h3FFFFFFF
`endif
`ifndef L2_ENABLE
@@ -61,7 +61,7 @@
`define CSR_LTID 12'h020
`define CSR_LWID 12'h021
`define CSR_GTID 12'h022
`define CSR_GTID 12'hF14 // reserved Hardware Thread ID (mhartid)
`define CSR_GWID 12'h023
`define CSR_GCID 12'h024
`define CSR_NT 12'h025
@@ -101,8 +101,8 @@
`endif
// Core Request Queue Size
`ifndef DREQQ_SIZE
`define DREQQ_SIZE `NUM_WARPS
`ifndef DCREQ_SIZE
`define DCREQ_SIZE `NUM_WARPS
`endif
// Miss Reserv Queue Knob
@@ -122,7 +122,7 @@
// Core Writeback Queue Size
`ifndef DCWBQ_SIZE
`define DCWBQ_SIZE `DREQQ_SIZE
`define DCWBQ_SIZE `DCREQ_SIZE
`endif
// Dram Writeback Queue Size
@@ -132,7 +132,7 @@
// Dram Fill Req Queue Size
`ifndef DDFQQ_SIZE
`define DDFQQ_SIZE `DREQQ_SIZE
`define DDFQQ_SIZE `DCREQ_SIZE
`endif
// Prefetcher
@@ -172,13 +172,13 @@
`endif
// Core Request Queue Size
`ifndef IREQQ_SIZE
`define IREQQ_SIZE `NUM_WARPS
`ifndef ICREQ_SIZE
`define ICREQ_SIZE `NUM_WARPS
`endif
// Miss Reserv Queue Knob
`ifndef IMRVQ_SIZE
`define IMRVQ_SIZE `IREQQ_SIZE
`define IMRVQ_SIZE `ICREQ_SIZE
`endif
// Dram Fill Rsp Queue Size
@@ -188,7 +188,7 @@
// Core Writeback Queue Size
`ifndef ICWBQ_SIZE
`define ICWBQ_SIZE `IREQQ_SIZE
`define ICWBQ_SIZE `ICREQ_SIZE
`endif
// Dram Writeback Queue Size
@@ -198,7 +198,7 @@
// Dram Fill Req Queue Size
`ifndef IDFQQ_SIZE
`define IDFQQ_SIZE `IREQQ_SIZE
`define IDFQQ_SIZE `ICREQ_SIZE
`endif
// Prefetcher
@@ -238,42 +238,13 @@
`endif
// Core Request Queue Size
`ifndef SREQQ_SIZE
`define SREQQ_SIZE `NUM_WARPS
`endif
// Miss Reserv Queue Knob
`ifndef SMRVQ_SIZE
`define SMRVQ_SIZE `SREQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`ifndef SDFPQ_SIZE
`define SDFPQ_SIZE 0
`ifndef SCREQ_SIZE
`define SCREQ_SIZE `NUM_WARPS
`endif
// Core Writeback Queue Size
`ifndef SCWBQ_SIZE
`define SCWBQ_SIZE `SREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef SDWBQ_SIZE
`define SDWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
`ifndef SDFQQ_SIZE
`define SDFQQ_SIZE 16
`endif
// Prefetcher
`ifndef SPRFQ_SIZE
`define SPRFQ_SIZE 4
`endif
`ifndef SPRFQ_STRIDE
`define SPRFQ_STRIDE 0
`define SCWBQ_SIZE `SCREQ_SIZE
`endif
// ======================== L2cache Configurable Knobs ========================
@@ -304,8 +275,8 @@
`endif
// Core Request Queue Size
`ifndef L2REQQ_SIZE
`define L2REQQ_SIZE 32
`ifndef L2CREQ_SIZE
`define L2CREQ_SIZE 32
`endif
// Miss Reserv Queue Knob
@@ -325,7 +296,7 @@
// Core Writeback Queue Size
`ifndef L2CWBQ_SIZE
`define L2CWBQ_SIZE `L2REQQ_SIZE
`define L2CWBQ_SIZE `L2CREQ_SIZE
`endif
// Dram Writeback Queue Size
@@ -335,7 +306,7 @@
// Dram Fill Req Queue Size
`ifndef L2DFQQ_SIZE
`define L2DFQQ_SIZE `L2REQQ_SIZE
`define L2DFQQ_SIZE `L2CREQ_SIZE
`endif
// Prefetcher
@@ -375,13 +346,13 @@
`endif
// Core Request Queue Size
`ifndef L3REQQ_SIZE
`define L3REQQ_SIZE 32
`ifndef L3CREQ_SIZE
`define L3CREQ_SIZE 32
`endif
// Miss Reserv Queue Knob
`ifndef L3MRVQ_SIZE
`define L3MRVQ_SIZE `L3REQQ_SIZE
`define L3MRVQ_SIZE `L3CREQ_SIZE
`endif
// Dram Fill Rsp Queue Size
@@ -396,7 +367,7 @@
// Core Writeback Queue Size
`ifndef L3CWBQ_SIZE
`define L3CWBQ_SIZE `L3REQQ_SIZE
`define L3CWBQ_SIZE `L3CREQ_SIZE
`endif
// Dram Writeback Queue Size
@@ -406,7 +377,7 @@
// Dram Fill Req Queue Size
`ifndef L3DFQQ_SIZE
`define L3DFQQ_SIZE `L3REQQ_SIZE
`define L3DFQQ_SIZE `L3CREQ_SIZE
`endif
// Prefetcher

8
hw/rtl/VX_dcache_io_arb.v
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@@ -22,15 +22,15 @@ module VX_dcache_io_arb (
VX_cache_core_rsp_if core_rsp_if
);
assign dcache_core_req_if.core_req_valid = core_req_if.core_req_valid & {`NUM_THREADS{~io_select}};
assign dcache_core_req_if.core_req_read = core_req_if.core_req_read;
assign dcache_core_req_if.core_req_write = core_req_if.core_req_write;
assign dcache_core_req_if.core_req_rw = core_req_if.core_req_rw;
assign dcache_core_req_if.core_req_byteen= core_req_if.core_req_byteen;
assign dcache_core_req_if.core_req_addr = core_req_if.core_req_addr;
assign dcache_core_req_if.core_req_data = core_req_if.core_req_data;
assign dcache_core_req_if.core_req_tag = core_req_if.core_req_tag;
assign io_core_req_if.core_req_valid = core_req_if.core_req_valid & {`NUM_THREADS{io_select}};
assign io_core_req_if.core_req_read = core_req_if.core_req_read;
assign io_core_req_if.core_req_write = core_req_if.core_req_write;
assign io_core_req_if.core_req_rw = core_req_if.core_req_rw;
assign io_core_req_if.core_req_byteen= core_req_if.core_req_byteen;
assign io_core_req_if.core_req_addr = core_req_if.core_req_addr;
assign io_core_req_if.core_req_data = core_req_if.core_req_data;
assign io_core_req_if.core_req_tag = core_req_if.core_req_tag;

2
hw/rtl/VX_decode.v
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@@ -115,7 +115,7 @@ module VX_decode(
assign is_split = is_gpgpu && (func3 == 2); // Goes to BE
assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE
assign join_if.is_join = is_join;
assign join_if.is_join = is_join && (| in_valid);
assign join_if.join_warp_num = in_warp_num;
assign frE_to_bckE_req_if.is_wspawn = is_wspawn;

75
hw/rtl/VX_define.vh
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@@ -10,6 +10,14 @@
///////////////////////////////////////////////////////////////////////////////
`ifndef NDEBUG
`define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
x \
/* verilator lint_on UNUSED */
`else
`define DEBUG_BLOCK(x)
`endif
`define DEBUG_BEGIN /* verilator lint_off UNUSED */
`define DEBUG_END /* verilator lint_on UNUSED */
@@ -44,6 +52,8 @@
`define MIN(x, y) ((x < y) ? (x) : (y))
`define MAX(x, y) ((x > y) ? (x) : (y))
`define UP(x) (((x) > 0) ? x : 1)
///////////////////////////////////////////////////////////////////////////////
`define NW_BITS (`LOG2UP(`NUM_WARPS))
@@ -61,11 +71,11 @@
///////////////////////////////////////////////////////////////////////////////
`define BYTE_EN_NO 3'h7
`define BYTE_EN_LB 3'h0
`define BYTE_EN_LH 3'h1
`define BYTE_EN_LW 3'h2
`define BYTE_EN_HB 3'h4
`define BYTE_EN_HH 3'h5
`define BYTE_EN_SB 3'h0
`define BYTE_EN_SH 3'h1
`define BYTE_EN_SW 3'h2
`define BYTE_EN_UB 3'h4
`define BYTE_EN_UH 3'h5
`define BYTE_EN_BITS 3
///////////////////////////////////////////////////////////////////////////////
@@ -126,16 +136,29 @@
///////////////////////////////////////////////////////////////////////////////
// Core request tag width pc, wb, rd, warp_num
`define CORE_REQ_TAG_WIDTH (32 + 2 + 5 + `NW_BITS)
// TAG sharing enable rd, warp_num
`define CORE_TAG_ID_BITS (5 + `NW_BITS)
`ifndef NDEBUG
// pc, wb, rd, warp_num
`define DEBUG_CORE_REQ_MDATA_WIDTH (32 + 2 + 5 + `NW_BITS)
`else
`define DEBUG_CORE_REQ_MDATA_WIDTH 0
`endif
////////////////////////// Dcache Configurable Knobs //////////////////////////
// Cache ID
`define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0)
// Core request address bits
`define DCORE_ADDR_WIDTH (32-`CLOG2(`DWORD_SIZE))
// Core request byte enable bits
`define DCORE_BYTEEN_WIDTH `DWORD_SIZE
// TAG sharing enable
`define DCORE_TAG_ID_BITS `LOG2UP(`DCREQ_SIZE)
// Core request tag bits
`define DCORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `DCORE_TAG_ID_BITS)
// DRAM request data bits
`define DDRAM_LINE_WIDTH (`DBANK_LINE_SIZE * 8)
@@ -143,6 +166,9 @@
// DRAM request address bits
`define DDRAM_ADDR_WIDTH (32 - `CLOG2(`DBANK_LINE_SIZE))
// DRAM byte enable bits
`define DDRAM_BYTEEN_WIDTH `DBANK_LINE_SIZE
// DRAM request tag bits
`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH
@@ -157,12 +183,27 @@
// Cache ID
`define ICACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 1)
// Core request address bits
`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE))
// Core request byte enable bits
`define ICORE_BYTEEN_WIDTH `DWORD_SIZE
// TAG sharing enable
`define ICORE_TAG_ID_BITS `LOG2UP(`ICREQ_SIZE)
// Core request tag bits
`define ICORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `ICORE_TAG_ID_BITS)
// DRAM request data bits
`define IDRAM_LINE_WIDTH (`IBANK_LINE_SIZE * 8)
// DRAM request address bits
`define IDRAM_ADDR_WIDTH (32 - `CLOG2(`IBANK_LINE_SIZE))
// DRAM byte enable bits
`define IDRAM_BYTEEN_WIDTH `IBANK_LINE_SIZE
// DRAM request tag bits
`define IDRAM_TAG_WIDTH `IDRAM_ADDR_WIDTH
@@ -174,8 +215,8 @@
// Cache ID
`define SCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 3)
// DRAM request data bits
`define SDRAM_LINE_WIDTH (`SBANK_LINE_SIZE * 8)
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define SNUM_REQUESTS `NUM_THREADS
// DRAM request address bits
`define SDRAM_ADDR_WIDTH (32 - `CLOG2(`SBANK_LINE_SIZE))
@@ -197,11 +238,14 @@
// DRAM request address bits
`define L2DRAM_ADDR_WIDTH (32 - `CLOG2(`L2BANK_LINE_SIZE))
// DRAM byte enable bits
`define L2DRAM_BYTEEN_WIDTH (`L2_ENABLE ? `L2BANK_LINE_SIZE : `DDRAM_BYTEEN_WIDTH)
// DRAM request tag bits
`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+`CLOG2(`NUM_CORES*2)))
// Snoop request tag bits
`define L2SNP_TAG_WIDTH ((`NUM_CLUSTERS > 1) ? `LOG2UP(`L3SNRQ_SIZE) : `L3SNP_TAG_WIDTH)
`define L2SNP_TAG_WIDTH (`L3_ENABLE ? `LOG2UP(`L3SNRQ_SIZE) : `L3SNP_TAG_WIDTH)
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define L2NUM_REQUESTS (2*`NUM_CORES)
@@ -217,8 +261,11 @@
// DRAM request address bits
`define L3DRAM_ADDR_WIDTH (32 - `CLOG2(`L3BANK_LINE_SIZE))
// DRAM byte enable bits
`define L3DRAM_BYTEEN_WIDTH (`L3_ENABLE ? `L3BANK_LINE_SIZE : `L2DRAM_BYTEEN_WIDTH)
// DRAM request tag bits
`define L3DRAM_TAG_WIDTH ((`NUM_CLUSTERS > 1) ? `L3DRAM_ADDR_WIDTH : `L2DRAM_TAG_WIDTH)
`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : `L2DRAM_TAG_WIDTH)
// Snoop request tag bits
`define L3SNP_TAG_WIDTH 16

89
hw/rtl/VX_dmem_ctrl.v
View File

@@ -25,21 +25,21 @@ module VX_dmem_ctrl # (
VX_cache_dram_rsp_if icache_dram_rsp_if
);
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.NUM_REQUESTS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) dcache_core_req_qual_if(), smem_core_req_if();
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.NUM_REQUESTS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) dcache_core_rsp_qual_if(), smem_core_rsp_if();
// use "case equality" to handle uninitialized entry
wire smem_select = ((dcache_core_req_if.core_req_addr[0][31:24] == `SHARED_MEM_TOP_ADDR) === 1'b1);
wire smem_select = ((dcache_core_req_if.core_req_addr[0] >= `BYTE_TO_WORD_ADDR(`SHARED_MEM_BASE_ADDR, `DWORD_SIZE)) === 1'b1);
VX_dcache_io_arb dcache_io_arb (
.io_select (smem_select),
@@ -59,20 +59,20 @@ module VX_dmem_ctrl # (
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQUESTS (`SNUM_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.REQQ_SIZE (`SREQQ_SIZE),
.MRVQ_SIZE (`SMRVQ_SIZE),
.DFPQ_SIZE (`SDFPQ_SIZE),
.CREQ_SIZE (`SCREQ_SIZE),
.MRVQ_SIZE (1),
.DFPQ_SIZE (0),
.SNRQ_SIZE (0),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (`SDWBQ_SIZE),
.DFQQ_SIZE (`SDFQQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.DWBQ_SIZE (0),
.DFQQ_SIZE (0),
.PRFQ_SIZE (0),
.PRFQ_STRIDE (0),
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (0),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS (`CORE_TAG_ID_BITS),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) gpu_smem (
.clk (clk),
@@ -80,8 +80,8 @@ module VX_dmem_ctrl # (
// Core request
.core_req_valid (smem_core_req_if.core_req_valid),
.core_req_read (smem_core_req_if.core_req_read),
.core_req_write (smem_core_req_if.core_req_write),
.core_req_rw (smem_core_req_if.core_req_rw),
.core_req_byteen (smem_core_req_if.core_req_byteen),
.core_req_addr (smem_core_req_if.core_req_addr),
.core_req_data (smem_core_req_if.core_req_data),
.core_req_tag (smem_core_req_if.core_req_tag),
@@ -94,21 +94,22 @@ module VX_dmem_ctrl # (
.core_rsp_ready (smem_core_rsp_if.core_rsp_ready),
// DRAM request
`UNUSED_PIN (dram_req_read),
`UNUSED_PIN (dram_req_write),
`UNUSED_PIN (dram_req_valid),
`UNUSED_PIN (dram_req_rw),
`UNUSED_PIN (dram_req_byteen),
`UNUSED_PIN (dram_req_addr),
`UNUSED_PIN (dram_req_data),
`UNUSED_PIN (dram_req_tag),
.dram_req_ready (1'b0),
.dram_req_ready (0),
// DRAM response
.dram_rsp_valid (1'b0),
.dram_rsp_valid (0),
.dram_rsp_data (0),
.dram_rsp_tag (`SDRAM_TAG_WIDTH'(0)),
.dram_rsp_tag (0),
`UNUSED_PIN (dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_valid (0),
.snp_req_addr (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
@@ -116,7 +117,7 @@ module VX_dmem_ctrl # (
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
.snp_rsp_ready (0),
// Snoop forward out
`UNUSED_PIN (snp_fwdout_valid),
@@ -138,7 +139,7 @@ module VX_dmem_ctrl # (
.WORD_SIZE (`DWORD_SIZE),
.NUM_REQUESTS (`DNUM_REQUESTS),
.STAGE_1_CYCLES (`DSTAGE_1_CYCLES),
.REQQ_SIZE (`DREQQ_SIZE),
.CREQ_SIZE (`DCREQ_SIZE),
.MRVQ_SIZE (`DMRVQ_SIZE),
.DFPQ_SIZE (`DDFPQ_SIZE),
.SNRQ_SIZE (`DSNRQ_SIZE),
@@ -150,8 +151,8 @@ module VX_dmem_ctrl # (
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS (`CORE_TAG_ID_BITS),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) gpu_dcache (
@@ -160,8 +161,8 @@ module VX_dmem_ctrl # (
// Core req
.core_req_valid (dcache_core_req_qual_if.core_req_valid),
.core_req_read (dcache_core_req_qual_if.core_req_read),
.core_req_write (dcache_core_req_qual_if.core_req_write),
.core_req_rw (dcache_core_req_qual_if.core_req_rw),
.core_req_byteen (dcache_core_req_qual_if.core_req_byteen),
.core_req_addr (dcache_core_req_qual_if.core_req_addr),
.core_req_data (dcache_core_req_qual_if.core_req_data),
.core_req_tag (dcache_core_req_qual_if.core_req_tag),
@@ -174,8 +175,9 @@ module VX_dmem_ctrl # (
.core_rsp_ready (dcache_core_rsp_qual_if.core_rsp_ready),
// DRAM request
.dram_req_read (dcache_dram_req_if.dram_req_read),
.dram_req_write (dcache_dram_req_if.dram_req_write),
.dram_req_valid (dcache_dram_req_if.dram_req_valid),
.dram_req_rw (dcache_dram_req_if.dram_req_rw),
.dram_req_byteen (dcache_dram_req_if.dram_req_byteen),
.dram_req_addr (dcache_dram_req_if.dram_req_addr),
.dram_req_data (dcache_dram_req_if.dram_req_data),
.dram_req_tag (dcache_dram_req_if.dram_req_tag),
@@ -218,7 +220,7 @@ module VX_dmem_ctrl # (
.WORD_SIZE (`IWORD_SIZE),
.NUM_REQUESTS (`INUM_REQUESTS),
.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
.REQQ_SIZE (`IREQQ_SIZE),
.CREQ_SIZE (`ICREQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (0),
@@ -230,8 +232,8 @@ module VX_dmem_ctrl # (
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (1),
.WRITE_ENABLE (0),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS (`CORE_TAG_ID_BITS),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) gpu_icache (
.clk (clk),
@@ -239,8 +241,8 @@ module VX_dmem_ctrl # (
// Core request
.core_req_valid (icache_core_req_if.core_req_valid),
.core_req_read (icache_core_req_if.core_req_read),
.core_req_write (icache_core_req_if.core_req_write),
.core_req_rw (icache_core_req_if.core_req_rw),
.core_req_byteen (icache_core_req_if.core_req_byteen),
.core_req_addr (icache_core_req_if.core_req_addr),
.core_req_data (icache_core_req_if.core_req_data),
.core_req_tag (icache_core_req_if.core_req_tag),
@@ -253,8 +255,9 @@ module VX_dmem_ctrl # (
.core_rsp_ready (icache_core_rsp_if.core_rsp_ready),
// DRAM Req
.dram_req_read (icache_dram_req_if.dram_req_read),
.dram_req_write (icache_dram_req_if.dram_req_write),
.dram_req_valid (icache_dram_req_if.dram_req_valid),
.dram_req_rw (icache_dram_req_if.dram_req_rw),
.dram_req_byteen (icache_dram_req_if.dram_req_byteen),
.dram_req_addr (icache_dram_req_if.dram_req_addr),
.dram_req_data (icache_dram_req_if.dram_req_data),
.dram_req_tag (icache_dram_req_if.dram_req_tag),
@@ -267,7 +270,7 @@ module VX_dmem_ctrl # (
.dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_valid (0),
.snp_req_addr (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
@@ -275,7 +278,7 @@ module VX_dmem_ctrl # (
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
.snp_rsp_ready (0),
// Snoop forward out
`UNUSED_PIN (snp_fwdout_valid),

15
hw/rtl/VX_dram_arb.v
View File

@@ -10,8 +10,9 @@ module VX_dram_arb #(
input wire reset,
// Core request
input wire [NUM_REQUESTS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][BANK_LINE_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
@@ -24,8 +25,9 @@ module VX_dram_arb #(
input wire [NUM_REQUESTS-1:0] core_rsp_ready,
// DRAM request
output wire dram_req_read,
output wire dram_req_write,
output wire dram_req_valid,
output wire dram_req_rw,
output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
@@ -47,8 +49,9 @@ module VX_dram_arb #(
end
end
assign dram_req_read = core_req_read [bus_req_sel];
assign dram_req_write = core_req_write [bus_req_sel];
assign dram_req_valid = core_req_valid [bus_req_sel];
assign dram_req_rw = core_req_rw [bus_req_sel];
assign dram_req_byteen= core_req_byteen [bus_req_sel];
assign dram_req_addr = core_req_addr [bus_req_sel];
assign dram_req_data = core_req_data [bus_req_sel];
assign dram_req_tag = {core_req_tag [bus_req_sel], (`REQS_BITS)'(bus_req_sel)};

63
hw/rtl/VX_icache_stage.v
View File

@@ -21,24 +21,48 @@ module VX_icache_stage #(
wire valid_inst = (| fe_inst_meta_fi.valid);
`DEBUG_BEGIN
wire [`CORE_REQ_TAG_WIDTH-1:0] core_req_tag = icache_req_if.core_req_tag;
wire [`CORE_REQ_TAG_WIDTH-1:0] core_rsp_tag = icache_rsp_if.core_rsp_tag;
wire [`ICORE_TAG_WIDTH-1:0] mem_req_tag = icache_req_if.core_req_tag;
wire [`ICORE_TAG_WIDTH-1:0] mem_rsp_tag = icache_rsp_if.core_rsp_tag;
`DEBUG_END
wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr;
wire mrq_full;
wire mrq_push = (| icache_req_if.core_req_valid) && icache_req_if.core_req_ready;
wire mrq_pop = (| icache_rsp_if.core_rsp_valid) && icache_rsp_if.core_rsp_ready;
assign mrq_read_addr = icache_rsp_if.core_rsp_tag[0][`LOG2UP(`ICREQ_SIZE)-1:0];
VX_indexable_queue #(
.DATAW (32 + `NW_BITS),
.SIZE (`ICREQ_SIZE)
) mem_req_queue (
.clk (clk),
.reset (reset),
.write_data ({fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num}),
.write_addr (mrq_write_addr),
.push (mrq_push),
.full (mrq_full),
.pop (mrq_pop),
.read_addr (mrq_read_addr),
.read_data ({fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num})
);
// Icache Request
assign icache_req_if.core_req_valid = valid_inst;
assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc;
assign icache_req_if.core_req_data = 0;
assign icache_req_if.core_req_read = `BYTE_EN_LW;
assign icache_req_if.core_req_write = `BYTE_EN_NO;
assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num};
assign icache_req_if.core_req_valid = valid_inst && ~mrq_full;
assign icache_req_if.core_req_rw = 0;
assign icache_req_if.core_req_byteen = 0;
assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc[31:2];
assign icache_req_if.core_req_data = 0;
`IGNORE_WARNINGS_BEGIN
wire[4:0] rsp_rd;
wire[1:0] rsp_wb;
`IGNORE_WARNINGS_END
// Can't accept new request
assign icache_stage_delay = mrq_full || ~icache_req_if.core_req_ready;
assign {fe_inst_meta_id.inst_pc, rsp_wb, rsp_rd, fe_inst_meta_id.warp_num} = icache_rsp_if.core_rsp_tag;
`ifndef NDEBUG
assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr};
`else
assign icache_req_if.core_req_tag = mrq_write_addr;
`endif
assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_data[0];
assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? valid_threads[fe_inst_meta_id.warp_num] : 0;
@@ -46,10 +70,7 @@ module VX_icache_stage #(
assign icache_stage_wid = fe_inst_meta_id.warp_num;
assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}};
// Cache can't accept request
assign icache_stage_delay = ~icache_req_if.core_req_ready;
// Core can't accept response
// Can't accept new response
assign icache_rsp_if.core_rsp_ready = ~total_freeze;
always @(posedge clk) begin
@@ -64,11 +85,11 @@ module VX_icache_stage #(
`ifdef DBG_PRINT_CORE_ICACHE
always_ff @(posedge clk) begin
if (icache_req_if.core_req_ready && icache_req_if.core_req_valid) begin
$display("%t: I%01d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, icache_req_if.core_req_tag, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin
$display("%t: I%01d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
end
if (icache_rsp_if.core_rsp_ready && icache_rsp_if.core_rsp_valid) begin
$display("%t: I%01d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, icache_rsp_if.core_rsp_tag, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction);
if (icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready) begin
$display("%t: I%01d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction);
end
end
`endif

159
hw/rtl/VX_lsu_unit.v
View File

@@ -47,33 +47,154 @@ module VX_lsu_unit #(
.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
);
wire core_req_rw = (use_mem_write != `BYTE_EN_NO);
reg [3:0] wmask;
always @(*) begin
case (use_mem_write[1:0])
0: begin
wmask = 4'b0001;
end
1: begin
wmask = 4'b0011;
end
default : begin
wmask = 4'b1111;
end
endcase
end
genvar i;
wire [`NUM_THREADS-1:0][4:0] mem_req_offset;
wire [`NUM_THREADS-1:0][29:0] mem_req_addr;
wire [`NUM_THREADS-1:0][3:0] mem_req_byteen;
wire [`NUM_THREADS-1:0][31:0] mem_req_data;
wire [`NUM_THREADS-1:0][4:0] mem_rsp_offset;
wire[2:0] core_rsp_mem_read;
for (i = 0; i < `NUM_THREADS; ++i) begin
always @(*) begin
case (core_req_rw ? use_mem_write[1:0] : use_mem_read[1:0])
2'b0: begin
case (use_address[i][1:0])
1: mem_req_offset[i] = 8;
2: mem_req_offset[i] = 16;
3: mem_req_offset[i] = 24;
default : mem_req_offset[i] = 0;
endcase
end
2'b1: begin
case (use_address[i][1:0])
2: mem_req_offset[i] = 16;
default : mem_req_offset[i] = 0;
endcase
end
default : begin
mem_req_offset[i] = 0;
end
endcase
end
assign mem_req_addr[i] = use_address[i][31:2];
assign mem_req_byteen[i] = (wmask << use_address[i][1:0]);
assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]);
end
reg [`NUM_THREADS-1:0] mem_rsp_mask[`DCREQ_SIZE-1:0];
wire [`LOG2UP(`DCREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr;
wire mrq_full;
wire mrq_push = (0 == core_req_rw) && (| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready;
wire mrq_pop_part = (| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready;
assign mrq_read_addr = dcache_rsp_if.core_rsp_tag[0][`LOG2UP(`DCREQ_SIZE)-1:0];
wire [`NUM_THREADS-1:0] mem_rsp_mask_next = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.core_rsp_valid;
wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_next);
always @(posedge clk) begin
if (reset) begin
//--
end else begin
if (mrq_push) begin
mem_rsp_mask[mrq_write_addr] <= use_valid;
end
if (mrq_pop_part) begin
mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_next;
end
end
end
VX_indexable_queue #(
.DATAW (32 + 2 + (`NUM_THREADS * 5) + `BYTE_EN_BITS + 5 + `NW_BITS),
.SIZE (`DCREQ_SIZE)
) mem_req_queue (
.clk (clk),
.reset (reset),
.write_data ({use_pc, use_wb, mem_req_offset, use_mem_read, use_rd, use_warp_num}),
.write_addr (mrq_write_addr),
.push (mrq_push),
.full (mrq_full),
.pop (mrq_pop),
.read_addr (mrq_read_addr),
.read_data ({mem_wb_if.pc, mem_wb_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_if.rd, mem_wb_if.warp_num})
);
// Core Request
assign dcache_req_if.core_req_valid = use_valid;
assign dcache_req_if.core_req_read = {`NUM_THREADS{use_mem_read}};
assign dcache_req_if.core_req_write = {`NUM_THREADS{use_mem_write}};
assign dcache_req_if.core_req_addr = use_address;
assign dcache_req_if.core_req_data = use_store_data;
assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num};
assign delay = ~dcache_req_if.core_req_ready;
assign dcache_req_if.core_req_valid = use_valid & {`NUM_THREADS{~mrq_full}};
assign dcache_req_if.core_req_rw = {`NUM_THREADS{core_req_rw}};
assign dcache_req_if.core_req_byteen= mem_req_byteen;
assign dcache_req_if.core_req_addr = mem_req_addr;
assign dcache_req_if.core_req_data = mem_req_data;
`ifndef NDEBUG
assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr};
`else
assign dcache_req_if.core_req_tag = mrq_write_addr;
`endif
// Can't accept new request
assign delay = mrq_full || ~dcache_req_if.core_req_ready;
// Core Response
assign mem_wb_if.valid = dcache_rsp_if.core_rsp_valid;
assign mem_wb_if.data = dcache_rsp_if.core_rsp_data;
assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
assign {mem_wb_if.pc, mem_wb_if.wb, mem_wb_if.rd, mem_wb_if.warp_num} = dcache_rsp_if.core_rsp_tag;
reg [`NUM_THREADS-1:0][31:0] core_rsp_data;
wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted;
for (i = 0; i < `NUM_THREADS; ++i) begin
assign rsp_data_shifted[i] = (dcache_rsp_if.core_rsp_data[i] >> mem_rsp_offset[i]);
always @(*) begin
case (core_rsp_mem_read)
`BYTE_EN_SB: core_rsp_data[i] = rsp_data_shifted[i][7] ? (rsp_data_shifted[i] | 32'hFFFFFF00) : (rsp_data_shifted[i] & 32'h000000FF);
`BYTE_EN_SH: core_rsp_data[i] = rsp_data_shifted[i][15] ? (rsp_data_shifted[i] | 32'hFFFF0000) : (rsp_data_shifted[i] & 32'h0000FFFF);
`BYTE_EN_UB: core_rsp_data[i] = (rsp_data_shifted[i] & 32'h000000FF);
`BYTE_EN_UH: core_rsp_data[i] = (rsp_data_shifted[i] & 32'h0000FFFF);
default : core_rsp_data[i] = rsp_data_shifted[i];
endcase
end
end
assign mem_wb_if.valid = dcache_rsp_if.core_rsp_valid;
assign mem_wb_if.data = core_rsp_data;
// Can't accept new response
assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
`ifdef DBG_PRINT_CORE_DCACHE
always_ff @(posedge clk) begin
if (dcache_req_if.core_req_ready && (| dcache_req_if.core_req_valid)) begin
$display("%t: D%01d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, use_valid, use_address, dcache_req_if.core_req_tag, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, use_store_data);
if ((| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready) begin
$display("%t: D%01d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, mem_req_byteen, mem_req_data);
end
if (dcache_rsp_if.core_rsp_ready && (| dcache_rsp_if.core_rsp_valid)) begin
$display("%t: D%01d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, dcache_rsp_if.core_rsp_tag, mem_wb_if.pc, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data);
if ((| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready) begin
$display("%t: D%01d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, mrq_read_addr, mem_wb_if.pc, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data);
end
end
`endif
endmodule
endmodule

25
hw/rtl/VX_scheduler.v
View File

@@ -14,12 +14,12 @@ module VX_scheduler (
);
reg[31:0] count_valid;
assign is_empty = count_valid == 0;
assign is_empty = (count_valid == 0);
reg[31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
wire valid_wb = (writeback_if.wb != 0) && (| writeback_if.valid) && (writeback_if.rd != 0);
wire wb_inc = (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0);
wire valid_wb = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0);
wire wb_inc = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0);
wire rs1_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rs1] != 0);
wire rs2_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rs2] != 0);
@@ -50,9 +50,7 @@ module VX_scheduler (
integer i, w;
wire[`NUM_THREADS-1:0] old_rename_mask = rename_table[writeback_if.warp_num][writeback_if.rd];
wire[`NUM_THREADS-1:0] invalidate_mask = ~writeback_if.valid;
wire[`NUM_THREADS-1:0] valid_wb_new_mask = old_rename_mask & invalidate_mask;
wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid;
always @(posedge clk) begin
if (reset) begin
@@ -63,21 +61,16 @@ module VX_scheduler (
end
end else begin
if (valid_wb) begin
rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
if (0 == valid_wb_new_mask) begin
count_valid <= count_valid - 1;
end
end
if (!schedule_delay && wb_inc) begin
rename_table[bckE_req_if.warp_num][bckE_req_if.rd] <= bckE_req_if.valid;
end
if (valid_wb
&& (0 == (rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid))) begin
count_valid <= count_valid - 1;
end
if (!schedule_delay && wb_inc) begin
count_valid <= count_valid + 1;
end
end
end
end

2
hw/rtl/VX_warp_sched.v
View File

@@ -285,7 +285,7 @@ module VX_warp_sched (
// wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num));
wire should_jal = (jal && (warp_to_schedule == jal_warp_num));
wire should_bra = (branch_dir && (warp_to_schedule == branch_warp_num));
wire should_bra = (branch_valid && branch_dir && (warp_to_schedule == branch_warp_num));
assign hazard = (should_jal || should_bra) && schedule;

14
hw/rtl/VX_writeback.v
View File

@@ -20,23 +20,23 @@ module VX_writeback (
output wire no_slot_csr
);
VX_wb_if writeback_tmp_if();
VX_wb_if writeback_tmp_if();
wire exec_wb = (inst_exec_wb_if.wb != 0) && (| inst_exec_wb_if.valid);
wire mem_wb = (mem_wb_if.wb != 0) && (| mem_wb_if.valid);
wire csr_wb = (csr_wb_if.wb != 0) && (| csr_wb_if.valid);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
assign no_slot_csr = csr_wb && exec_wb;
assign no_slot_exec = 0;
assign writeback_tmp_if.data = exec_wb ? inst_exec_wb_if.data :
csr_wb ? csr_wb_if.data :
mem_wb ? mem_wb_if.data :
mem_wb ? mem_wb_if.data :
0;
assign writeback_tmp_if.valid = exec_wb ? inst_exec_wb_if.valid :
csr_wb ? csr_wb_if.valid :
csr_wb ? csr_wb_if.valid :
mem_wb ? mem_wb_if.valid :
0;
@@ -51,13 +51,13 @@ module VX_writeback (
0;
assign writeback_tmp_if.warp_num = exec_wb ? inst_exec_wb_if.warp_num :
csr_wb ? csr_wb_if.warp_num :
csr_wb ? csr_wb_if.warp_num :
mem_wb ? mem_wb_if.warp_num :
0;
assign writeback_tmp_if.pc = exec_wb ? inst_exec_wb_if.pc :
csr_wb ? 32'hdeadbeef :
mem_wb ? mem_wb_if.pc :
csr_wb ? 32'hdeadbeef :
mem_wb ? mem_wb_if.pc :
32'hdeadbeef;
wire zero = 0;

120
hw/rtl/Vortex.v
View File

@@ -5,65 +5,67 @@ module Vortex #(
parameter CORE_ID = 0
) (
// Clock
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// DRAM Dcache request
output wire D_dram_req_read,
output wire D_dram_req_write,
output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr,
output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data,
output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag,
input wire D_dram_req_ready,
output wire D_dram_req_valid,
output wire D_dram_req_rw,
output wire [`DDRAM_BYTEEN_WIDTH-1:0] D_dram_req_byteen,
output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr,
output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data,
output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag,
input wire D_dram_req_ready,
// DRAM Dcache reponse
input wire D_dram_rsp_valid,
input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data,
input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag,
output wire D_dram_rsp_ready,
input wire D_dram_rsp_valid,
input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data,
input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag,
output wire D_dram_rsp_ready,
// DRAM Icache request
output wire I_dram_req_read,
output wire I_dram_req_write,
output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr,
output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data,
output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag,
input wire I_dram_req_ready,
output wire I_dram_req_valid,
output wire I_dram_req_rw,
output wire [`IDRAM_BYTEEN_WIDTH-1:0] I_dram_req_byteen,
output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr,
output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data,
output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag,
input wire I_dram_req_ready,
// DRAM Icache response
input wire I_dram_rsp_valid,
input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data,
input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag,
output wire I_dram_rsp_ready,
input wire I_dram_rsp_valid,
input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data,
input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag,
output wire I_dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
input wire snp_req_valid,
input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
output wire snp_rsp_valid,
output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
output wire snp_rsp_valid,
output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// I/O request
output wire io_req_read,
output wire io_req_write,
output wire[31:0] io_req_addr,
output wire[31:0] io_req_data,
output wire[`BYTE_EN_BITS-1:0] io_req_byteen,
output wire[`CORE_REQ_TAG_WIDTH-1:0] io_req_tag,
input wire io_req_ready,
output wire io_req_valid,
output wire io_req_rw,
output wire[`DCORE_BYTEEN_WIDTH-1:0] io_req_byteen,
output wire[`DCORE_ADDR_WIDTH-1:0] io_req_addr,
output wire[31:0] io_req_data,
output wire[`DCORE_TAG_WIDTH-1:0] io_req_tag,
input wire io_req_ready,
// I/O response
input wire io_rsp_valid,
input wire[31:0] io_rsp_data,
input wire[`CORE_REQ_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
input wire io_rsp_valid,
input wire[31:0] io_rsp_data,
input wire[`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// Status
output wire busy,
output wire ebreak
output wire busy,
output wire ebreak
);
`DEBUG_BEGIN
wire scheduler_empty;
@@ -78,15 +80,15 @@ module Vortex #(
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) dcache_core_req_if(), io_core_req_if(), dcache_io_core_req_if();
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) dcache_core_rsp_if(), io_core_rsp_if(), dcache_io_core_rsp_if();
VX_cache_dram_req_if #(
@@ -100,8 +102,9 @@ module Vortex #(
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_rsp_if();
assign D_dram_req_write = dcache_dram_req_if.dram_req_write;
assign D_dram_req_read = dcache_dram_req_if.dram_req_read;
assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid;
assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw;
assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen;
assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
assign D_dram_req_data = dcache_dram_req_if.dram_req_data;
assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag;
@@ -112,11 +115,11 @@ module Vortex #(
assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag;
assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready;
assign io_req_read = (io_core_req_if.core_req_read[0] != `BYTE_EN_NO);
assign io_req_write = (io_core_req_if.core_req_write[0] != `BYTE_EN_NO);
assign io_req_valid = io_core_req_if.core_req_valid[0];
assign io_req_rw = io_core_req_if.core_req_rw[0];
assign io_req_byteen = io_core_req_if.core_req_byteen[0];
assign io_req_addr = io_core_req_if.core_req_addr[0];
assign io_req_data = io_core_req_if.core_req_data[0];
assign io_req_byteen = io_req_read ? io_core_req_if.core_req_read[0] : io_core_req_if.core_req_write[0];
assign io_req_tag = io_core_req_if.core_req_tag[0];
assign io_core_req_if.core_req_ready = io_req_ready;
@@ -129,15 +132,15 @@ module Vortex #(
VX_cache_core_req_if #(
.NUM_REQUESTS(`INUM_REQUESTS),
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) icache_core_req_if();
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`INUM_REQUESTS),
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) icache_core_rsp_if();
VX_cache_dram_req_if #(
@@ -151,8 +154,9 @@ module Vortex #(
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_rsp_if();
assign I_dram_req_write = icache_dram_req_if.dram_req_write;
assign I_dram_req_read = icache_dram_req_if.dram_req_read;
assign I_dram_req_valid = icache_dram_req_if.dram_req_valid;
assign I_dram_req_rw = icache_dram_req_if.dram_req_rw;
assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen;
assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
assign I_dram_req_data = icache_dram_req_if.dram_req_data;
assign I_dram_req_tag = icache_dram_req_if.dram_req_tag;
@@ -267,7 +271,7 @@ module Vortex #(
);
// use "case equality" to handle uninitialized address value
wire io_select = ((dcache_io_core_req_if.core_req_addr[0] >= `IO_BUS_BASE_ADDR) === 1'b1);
wire io_select = ((dcache_io_core_req_if.core_req_addr[0] >= `BYTE_TO_WORD_ADDR(`IO_BUS_BASE_ADDR, `DWORD_SIZE)) === 1'b1);
VX_dcache_io_arb dcache_io_arb (
.io_select (io_select),

170
hw/rtl/Vortex_Cluster.v
View File

@@ -5,55 +5,57 @@ module Vortex_Cluster #(
parameter CLUSTER_ID = 0
) (
// Clock
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// DRAM request
output wire dram_req_read,
output wire dram_req_write,
output wire[`L2DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire[`L2DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire[`L2DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
output wire dram_req_valid,
output wire dram_req_rw,
output wire[`L2DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen,
output wire[`L2DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire[`L2DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire[`L2DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire[`L2DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire[`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// DRAM response
input wire dram_rsp_valid,
input wire[`L2DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire[`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire[`L2DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire[`L2SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
input wire snp_req_valid,
input wire[`L2DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire[`L2SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire[`L2SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
output wire snp_rsp_valid,
output wire[`L2SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// I/O request
output wire io_req_read,
output wire io_req_write,
output wire[31:0] io_req_addr,
output wire[31:0] io_req_data,
output wire[`BYTE_EN_BITS-1:0] io_req_byteen,
output wire[`CORE_REQ_TAG_WIDTH-1:0] io_req_tag,
input wire io_req_ready,
output wire io_req_valid,
output wire io_req_rw,
output wire[`DCORE_BYTEEN_WIDTH-1:0] io_req_byteen,
output wire[`DCORE_ADDR_WIDTH-1:0] io_req_addr,
output wire[31:0] io_req_data,
output wire[`DCORE_TAG_WIDTH-1:0] io_req_tag,
input wire io_req_ready,
// I/O response
input wire io_rsp_valid,
input wire[31:0] io_rsp_data,
input wire[`CORE_REQ_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
input wire io_rsp_valid,
input wire[31:0] io_rsp_data,
input wire[`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// Status
output wire busy,
output wire ebreak
output wire busy,
output wire ebreak
);
wire[`NUM_CORES-1:0] per_core_D_dram_req_read;
wire[`NUM_CORES-1:0] per_core_D_dram_req_write;
wire[`NUM_CORES-1:0] per_core_D_dram_req_valid;
wire[`NUM_CORES-1:0] per_core_D_dram_req_rw;
wire[`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_D_dram_req_byteen;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_D_dram_req_addr;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_req_data;
wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_req_tag;
@@ -64,7 +66,9 @@ module Vortex_Cluster #(
wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_rsp_tag;
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
wire[`NUM_CORES-1:0] per_core_I_dram_req_read;
wire[`NUM_CORES-1:0] per_core_I_dram_req_valid;
wire[`NUM_CORES-1:0] per_core_I_dram_req_rw;
wire[`NUM_CORES-1:0][`IDRAM_BYTEEN_WIDTH-1:0] per_core_I_dram_req_byteen;
wire[`NUM_CORES-1:0][`IDRAM_ADDR_WIDTH-1:0] per_core_I_dram_req_addr;
wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_req_data;
wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_req_tag;
@@ -85,12 +89,12 @@ module Vortex_Cluster #(
wire[`NUM_CORES-1:0] per_core_snp_rsp_ready;
`IGNORE_WARNINGS_BEGIN
wire[`NUM_CORES-1:0] per_core_io_req_read;
wire[`NUM_CORES-1:0] per_core_io_req_write;
wire[`NUM_CORES-1:0][31:0] per_core_io_req_addr;
wire[`NUM_CORES-1:0][31:0] per_core_io_req_data;
wire[`NUM_CORES-1:0][`BYTE_EN_BITS-1:0] per_core_io_req_byteen;
wire[`NUM_CORES-1:0][`CORE_REQ_TAG_WIDTH-1:0] per_core_io_req_tag;
wire[`NUM_CORES-1:0] per_core_io_req_valid;
wire[`NUM_CORES-1:0] per_core_io_req_rw;
wire[`NUM_CORES-1:0][`DCORE_BYTEEN_WIDTH-1:0] per_core_io_req_byteen;
wire[`NUM_CORES-1:0][`DCORE_ADDR_WIDTH-1:0] per_core_io_req_addr;
wire[`NUM_CORES-1:0][31:0] per_core_io_req_data;
wire[`NUM_CORES-1:0][`DCORE_TAG_WIDTH-1:0] per_core_io_req_tag;
wire[`NUM_CORES-1:0] per_core_io_rsp_ready;
`IGNORE_WARNINGS_END
@@ -105,8 +109,9 @@ module Vortex_Cluster #(
) vortex_core (
.clk (clk),
.reset (reset),
.D_dram_req_read (per_core_D_dram_req_read [i]),
.D_dram_req_write (per_core_D_dram_req_write [i]),
.D_dram_req_valid (per_core_D_dram_req_valid [i]),
.D_dram_req_rw (per_core_D_dram_req_rw [i]),
.D_dram_req_byteen (per_core_D_dram_req_byteen [i]),
.D_dram_req_addr (per_core_D_dram_req_addr [i]),
.D_dram_req_data (per_core_D_dram_req_data [i]),
.D_dram_req_tag (per_core_D_dram_req_tag [i]),
@@ -116,8 +121,9 @@ module Vortex_Cluster #(
.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
.I_dram_req_read (per_core_I_dram_req_read [i]),
`UNUSED_PIN (I_dram_req_write),
.I_dram_req_valid (per_core_I_dram_req_valid [i]),
.I_dram_req_rw (per_core_I_dram_req_rw [i]),
.I_dram_req_byteen (per_core_I_dram_req_byteen [i]),
.I_dram_req_addr (per_core_I_dram_req_addr [i]),
.I_dram_req_data (per_core_I_dram_req_data [i]),
.I_dram_req_tag (per_core_I_dram_req_tag [i]),
@@ -136,11 +142,11 @@ module Vortex_Cluster #(
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.io_req_read (per_core_io_req_read [i]),
.io_req_write (per_core_io_req_write [i]),
.io_req_addr (per_core_io_req_addr [i]),
.io_req_data (per_core_io_req_data [i]),
.io_req_valid (per_core_io_req_valid [i]),
.io_req_rw (per_core_io_req_rw [i]),
.io_req_byteen (per_core_io_req_byteen [i]),
.io_req_addr (per_core_io_req_addr [i]),
.io_req_data (per_core_io_req_data [i]),
.io_req_tag (per_core_io_req_tag [i]),
.io_req_ready (io_req_ready),
@@ -154,8 +160,9 @@ module Vortex_Cluster #(
);
end
assign io_req_read = per_core_io_req_read[0];
assign io_req_write = per_core_io_req_write[0];
assign io_req_valid = per_core_io_req_valid[0];
assign io_req_rw = per_core_io_req_rw[0];
assign io_req_byteen = per_core_io_req_byteen[0];
assign io_req_addr = per_core_io_req_addr[0];
assign io_req_data = per_core_io_req_data[0];
assign io_req_byteen = per_core_io_req_byteen[0];
@@ -171,9 +178,9 @@ module Vortex_Cluster #(
// L2 Cache ///////////////////////////////////////////////////////////
wire[`L2NUM_REQUESTS-1:0] l2_core_req_valid;
wire[`L2NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] l2_core_req_write;
wire[`L2NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] l2_core_req_read;
wire[`L2NUM_REQUESTS-1:0][31:0] l2_core_req_addr;
wire[`L2NUM_REQUESTS-1:0] l2_core_req_rw;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_BYTEEN_WIDTH-1:0] l2_core_req_byteen;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] l2_core_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_req_data;
wire l2_core_req_ready;
@@ -193,17 +200,17 @@ module Vortex_Cluster #(
wire[`NUM_CORES-1:0] l2_snp_fwdin_ready;
for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
assign l2_core_req_valid [i] = (per_core_D_dram_req_read[(i/2)] | per_core_D_dram_req_write[(i/2)]);
assign l2_core_req_valid [i+1] = per_core_I_dram_req_read[(i/2)];
assign l2_core_req_valid [i] = per_core_D_dram_req_valid[(i/2)];
assign l2_core_req_valid [i+1] = per_core_I_dram_req_valid[(i/2)];
assign l2_core_req_read [i] = per_core_D_dram_req_read[(i/2)] ? `BYTE_EN_LW : `BYTE_EN_NO;
assign l2_core_req_read [i+1] = per_core_I_dram_req_read[(i/2)] ? `BYTE_EN_LW : `BYTE_EN_NO;
assign l2_core_req_rw [i] = per_core_D_dram_req_rw[(i/2)];
assign l2_core_req_rw [i+1] = per_core_I_dram_req_rw[(i/2)];
assign l2_core_req_write [i] = per_core_D_dram_req_write[(i/2)] ? `BYTE_EN_LW : `BYTE_EN_NO;
assign l2_core_req_write [i+1] = `BYTE_EN_NO;
assign l2_core_req_byteen [i] = per_core_D_dram_req_byteen[(i/2)];
assign l2_core_req_byteen [i+1] = per_core_I_dram_req_byteen[(i/2)];
assign l2_core_req_addr [i] = {per_core_D_dram_req_addr[(i/2)], {`LOG2UP(`DBANK_LINE_SIZE){1'b0}}};
assign l2_core_req_addr [i+1] = {per_core_I_dram_req_addr[(i/2)], {`LOG2UP(`IBANK_LINE_SIZE){1'b0}}};
assign l2_core_req_addr [i] = per_core_D_dram_req_addr[(i/2)];
assign l2_core_req_addr [i+1] = per_core_I_dram_req_addr[(i/2)];
assign l2_core_req_data [i] = per_core_D_dram_req_data[(i/2)];
assign l2_core_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
@@ -243,7 +250,7 @@ module Vortex_Cluster #(
.WORD_SIZE (`L2WORD_SIZE),
.NUM_REQUESTS (`L2NUM_REQUESTS),
.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
.REQQ_SIZE (`L2REQQ_SIZE),
.CREQ_SIZE (`L2CREQ_SIZE),
.MRVQ_SIZE (`L2MRVQ_SIZE),
.DFPQ_SIZE (`L2DFPQ_SIZE),
.SNRQ_SIZE (`L2SNRQ_SIZE),
@@ -267,8 +274,8 @@ module Vortex_Cluster #(
// Core request
.core_req_valid (l2_core_req_valid),
.core_req_read (l2_core_req_read),
.core_req_write (l2_core_req_write),
.core_req_rw (l2_core_req_rw),
.core_req_byteen (l2_core_req_byteen),
.core_req_addr (l2_core_req_addr),
.core_req_data (l2_core_req_data),
.core_req_tag (l2_core_req_tag),
@@ -281,8 +288,9 @@ module Vortex_Cluster #(
.core_rsp_ready (l2_core_rsp_ready),
// DRAM request
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
@@ -319,8 +327,9 @@ module Vortex_Cluster #(
end else begin
wire[`L2NUM_REQUESTS-1:0] arb_core_req_read;
wire[`L2NUM_REQUESTS-1:0] arb_core_req_write;
wire[`L2NUM_REQUESTS-1:0] arb_core_req_valid;
wire[`L2NUM_REQUESTS-1:0] arb_core_req_rw;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_BYTEEN_WIDTH-1:0] arb_core_req_byteen;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] arb_core_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] arb_core_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] arb_core_req_data;
@@ -341,11 +350,14 @@ module Vortex_Cluster #(
wire[`NUM_CORES-1:0] arb_snp_fwdin_ready;
for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
assign arb_core_req_read [i] = per_core_D_dram_req_read[(i/2)];
assign arb_core_req_read [i+1] = per_core_I_dram_req_read[(i/2)];
assign arb_core_req_valid [i] = per_core_D_dram_req_valid[(i/2)];
assign arb_core_req_valid [i+1] = per_core_I_dram_req_valid[(i/2)];
assign arb_core_req_write [i] = per_core_D_dram_req_write[(i/2)];
assign arb_core_req_write [i+1] = 0;
assign arb_core_req_rw [i] = per_core_D_dram_req_rw[(i/2)];
assign arb_core_req_rw [i+1] = per_core_I_dram_req_rw[(i/2)];
assign arb_core_req_byteen[i] = per_core_D_dram_req_byteen[(i/2)];
assign arb_core_req_byteen[i+1] = per_core_I_dram_req_byteen[(i/2)];
assign arb_core_req_addr [i] = per_core_D_dram_req_addr[(i/2)];
assign arb_core_req_addr [i+1] = per_core_I_dram_req_addr[(i/2)];
@@ -421,8 +433,9 @@ module Vortex_Cluster #(
.reset (reset),
// Core request
.core_req_read (arb_core_req_read),
.core_req_write (arb_core_req_write),
.core_req_valid (arb_core_req_valid),
.core_req_rw (arb_core_req_rw),
.core_req_byteen (arb_core_req_byteen),
.core_req_addr (arb_core_req_addr),
.core_req_data (arb_core_req_data),
.core_req_tag (arb_core_req_tag),
@@ -435,8 +448,9 @@ module Vortex_Cluster #(
.core_rsp_ready (arb_core_rsp_ready),
// DRAM request
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),

141
hw/rtl/Vortex_Socket.v
View File

@@ -3,52 +3,53 @@
module Vortex_Socket (
// Clock
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// DRAM request
output wire dram_req_read,
output wire dram_req_write,
output wire[`L3DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire[`L3DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire[`L3DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
output wire dram_req_valid,
output wire dram_req_rw,
output wire[`L3DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen,
output wire[`L3DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire[`L3DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire[`L3DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire[`L3DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire[`L3DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
input wire dram_rsp_valid,
input wire[`L3DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire[`L3DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire[`L3DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire[`L3SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
input wire snp_req_valid,
input wire[`L3DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire[`L3SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire[`L3SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
output wire snp_rsp_valid,
output wire[`L3SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// I/O request
output wire io_req_read,
output wire io_req_write,
output wire[31:0] io_req_addr,
output wire[31:0] io_req_data,
output wire[`BYTE_EN_BITS-1:0] io_req_byteen,
output wire[`CORE_REQ_TAG_WIDTH-1:0] io_req_tag,
input wire io_req_ready,
output wire io_req_valid,
output wire io_req_rw,
output wire[`DCORE_BYTEEN_WIDTH-1:0] io_req_byteen,
output wire[`DCORE_ADDR_WIDTH-1:0] io_req_addr,
output wire[31:0] io_req_data,
output wire[`DCORE_TAG_WIDTH-1:0] io_req_tag,
input wire io_req_ready,
// I/O response
input wire io_rsp_valid,
input wire[31:0] io_rsp_data,
input wire[`CORE_REQ_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
input wire io_rsp_valid,
input wire[31:0] io_rsp_data,
input wire[`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// Status
output wire busy,
output wire ebreak
output wire busy,
output wire ebreak
);
if (`NUM_CLUSTERS == 1) begin
@@ -58,8 +59,9 @@ module Vortex_Socket (
.clk (clk),
.reset (reset),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
@@ -79,11 +81,11 @@ module Vortex_Socket (
.snp_rsp_tag (snp_rsp_tag),
.snp_rsp_ready (snp_rsp_ready),
.io_req_read (io_req_read),
.io_req_write (io_req_write),
.io_req_valid (io_req_valid),
.io_req_rw (io_req_rw),
.io_req_byteen (io_req_byteen),
.io_req_addr (io_req_addr),
.io_req_data (io_req_data),
.io_req_byteen (io_req_byteen),
.io_req_tag (io_req_tag),
.io_req_ready (io_req_ready),
@@ -98,8 +100,9 @@ module Vortex_Socket (
end else begin
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag;
@@ -120,12 +123,12 @@ module Vortex_Socket (
wire[`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready;
`IGNORE_WARNINGS_BEGIN
wire[`NUM_CLUSTERS-1:0] per_cluster_io_req_read;
wire[`NUM_CLUSTERS-1:0] per_cluster_io_req_write;
wire[`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_addr;
wire[`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data;
wire[`NUM_CLUSTERS-1:0][`BYTE_EN_BITS-1:0] per_cluster_io_req_byteen;
wire[`NUM_CLUSTERS-1:0][`CORE_REQ_TAG_WIDTH-1:0] per_cluster_io_req_tag;
wire[`NUM_CLUSTERS-1:0] per_cluster_io_req_valid;
wire[`NUM_CLUSTERS-1:0] per_cluster_io_req_rw;
wire[`NUM_CLUSTERS-1:0][`DCORE_BYTEEN_WIDTH-1:0] per_cluster_io_req_byteen;
wire[`NUM_CLUSTERS-1:0][`DCORE_ADDR_WIDTH-1:0] per_cluster_io_req_addr;
wire[`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data;
wire[`NUM_CLUSTERS-1:0][`DCORE_TAG_WIDTH-1:0] per_cluster_io_req_tag;
wire[`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready;
`IGNORE_WARNINGS_END
@@ -141,8 +144,9 @@ module Vortex_Socket (
.clk (clk),
.reset (reset),
.dram_req_write (per_cluster_dram_req_write [i]),
.dram_req_read (per_cluster_dram_req_read [i]),
.dram_req_valid (per_cluster_dram_req_valid [i]),
.dram_req_rw (per_cluster_dram_req_rw [i]),
.dram_req_byteen (per_cluster_dram_req_byteen[i]),
.dram_req_addr (per_cluster_dram_req_addr [i]),
.dram_req_data (per_cluster_dram_req_data [i]),
.dram_req_tag (per_cluster_dram_req_tag [i]),
@@ -162,11 +166,11 @@ module Vortex_Socket (
.snp_rsp_tag (per_cluster_snp_rsp_tag [i]),
.snp_rsp_ready (per_cluster_snp_rsp_ready [i]),
.io_req_read (per_cluster_io_req_read [i]),
.io_req_write (per_cluster_io_req_write [i]),
.io_req_addr (per_cluster_io_req_addr [i]),
.io_req_data (per_cluster_io_req_data [i]),
.io_req_valid (per_cluster_io_req_valid [i]),
.io_req_rw (per_cluster_io_req_rw [i]),
.io_req_byteen (per_cluster_io_req_byteen [i]),
.io_req_addr (per_cluster_io_req_addr [i]),
.io_req_data (per_cluster_io_req_data [i]),
.io_req_tag (per_cluster_io_req_tag [i]),
.io_req_ready (io_req_ready),
@@ -180,11 +184,11 @@ module Vortex_Socket (
);
end
assign io_req_read = per_cluster_io_req_read[0];
assign io_req_write = per_cluster_io_req_write[0];
assign io_req_valid = per_cluster_io_req_valid[0];
assign io_req_rw = per_cluster_io_req_rw[0];
assign io_req_byteen = per_cluster_io_req_byteen[0];
assign io_req_addr = per_cluster_io_req_addr[0];
assign io_req_data = per_cluster_io_req_data[0];
assign io_req_byteen = per_cluster_io_req_byteen[0];
assign io_req_tag = per_cluster_io_req_tag[0];
assign io_rsp_ready = per_cluster_io_rsp_ready[0];
@@ -195,9 +199,9 @@ module Vortex_Socket (
// L3 Cache ///////////////////////////////////////////////////////////
wire[`L3NUM_REQUESTS-1:0] l3_core_req_valid;
wire[`L3NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] l3_core_req_read;
wire[`L3NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] l3_core_req_write;
wire[`L3NUM_REQUESTS-1:0][31:0] l3_core_req_addr;
wire[`L3NUM_REQUESTS-1:0] l3_core_req_rw;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag;
@@ -217,10 +221,10 @@ module Vortex_Socket (
for (i = 0; i < `L3NUM_REQUESTS; i++) begin
// Core Request
assign l3_core_req_valid [i] = (per_cluster_dram_req_read [i] | per_cluster_dram_req_write [i]);
assign l3_core_req_read [i] = per_cluster_dram_req_read [i] ? `BYTE_EN_LW : `BYTE_EN_NO;
assign l3_core_req_write [i] = per_cluster_dram_req_write [i] ? `BYTE_EN_LW : `BYTE_EN_NO;
assign l3_core_req_addr [i] = {per_cluster_dram_req_addr [i], {`LOG2UP(`L2BANK_LINE_SIZE){1'b0}}};
assign l3_core_req_valid [i] = per_cluster_dram_req_valid [i];
assign l3_core_req_rw [i] = per_cluster_dram_req_rw [i];
assign l3_core_req_byteen[i] = per_cluster_dram_req_byteen[i];
assign l3_core_req_addr [i] = per_cluster_dram_req_addr [i];
assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i];
assign l3_core_req_data [i] = per_cluster_dram_req_data [i];
@@ -251,7 +255,7 @@ module Vortex_Socket (
.WORD_SIZE (`L3WORD_SIZE),
.NUM_REQUESTS (`L3NUM_REQUESTS),
.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
.REQQ_SIZE (`L3REQQ_SIZE),
.CREQ_SIZE (`L3CREQ_SIZE),
.MRVQ_SIZE (`L3MRVQ_SIZE),
.DFPQ_SIZE (`L3DFPQ_SIZE),
.SNRQ_SIZE (`L3SNRQ_SIZE),
@@ -275,8 +279,8 @@ module Vortex_Socket (
// Core request
.core_req_valid (l3_core_req_valid),
.core_req_read (l3_core_req_read),
.core_req_write (l3_core_req_write),
.core_req_rw (l3_core_req_rw),
.core_req_byteen (l3_core_req_byteen),
.core_req_addr (l3_core_req_addr),
.core_req_data (l3_core_req_data),
.core_req_tag (l3_core_req_tag),
@@ -289,8 +293,9 @@ module Vortex_Socket (
.core_rsp_ready (l3_core_rsp_ready),
// DRAM request
.dram_req_write (dram_req_write),
.dram_req_read (dram_req_read),
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
@@ -328,8 +333,8 @@ module Vortex_Socket (
`ifdef DBG_PRINT_DRAM
always_ff @(posedge clk) begin
if ((dram_req_read || dram_req_write) && dram_req_ready) begin
$display("%t: DRAM req: w=%b addr=%0h, tag=%0h, data=%0h", $time, dram_req_write, {dram_req_addr, `CLOG2(`GLOBAL_BLOCK_SIZE)'(0)}, dram_req_tag, dram_req_data);
if (dram_req_valid && dram_req_ready) begin
$display("%t: DRAM req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, dram_req_rw, {dram_req_addr, `CLOG2(`GLOBAL_BLOCK_SIZE)'(0)}, dram_req_tag, dram_req_byteen, dram_req_data);
end
if (dram_rsp_valid && dram_rsp_ready) begin
$display("%t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data);

195
hw/rtl/cache/VX_bank.v vendored
View File

@@ -18,7 +18,7 @@ module VX_bank #(
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 0,
parameter CREQ_SIZE = 0,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 0,
// Dram Fill Rsp Queue Size
@@ -56,13 +56,13 @@ module VX_bank #(
input wire reset,
// Core Request
input wire [NUM_REQUESTS-1:0] core_req_valids,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
// Core Response
output wire core_rsp_valid,
@@ -84,6 +84,7 @@ module VX_bank #(
// Dram WB Requests
output wire dram_wb_req_valid,
output wire [BANK_LINE_SIZE-1:0] dram_wb_req_byteen,
output wire [`LINE_ADDR_WIDTH-1:0] dram_wb_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_wb_req_data,
input wire dram_wb_req_ready,
@@ -99,31 +100,34 @@ module VX_bank #(
input wire snp_rsp_ready
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
wire[31:0] debug_use_pc_st0;
wire[1:0] debug_wb_st0;
wire[4:0] debug_rd_st0;
wire[`NW_BITS-1:0] debug_warp_num_st0;
wire[2:0] debug_mem_read_st0;
wire[2:0] debug_mem_write_st0;
wire debug_rw_st0;
wire[WORD_SIZE-1:0] debug_byteen_st0;
wire[`REQS_BITS-1:0] debug_tid_st0;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0;
wire[31:0] debug_use_pc_st1e;
wire[1:0] debug_wb_st1e;
wire[4:0] debug_rd_st1e;
wire[`NW_BITS-1:0] debug_warp_num_st1e;
wire[2:0] debug_mem_read_st1e;
wire[2:0] debug_mem_write_st1e;
wire debug_rw_st1e;
wire[WORD_SIZE-1:0] debug_byteen_st1e;
wire[`REQS_BITS-1:0] debug_tid_st1e;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1e;
wire[31:0] debug_use_pc_st2;
wire[1:0] debug_wb_st2;
wire[4:0] debug_rd_st2;
wire[`NW_BITS-1:0] debug_warp_num_st2;
wire[2:0] debug_mem_read_st2;
wire[2:0] debug_mem_write_st2;
wire debug_rw_st2;
wire[WORD_SIZE-1:0] debug_byteen_st2;
wire[`REQS_BITS-1:0] debug_tid_st2;
`DEBUG_END
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2;
)
wire snrq_pop;
wire snrq_empty;
@@ -177,19 +181,19 @@ module VX_bank #(
wire reqq_empty;
wire reqq_full;
wire reqq_req_st0;
wire[`REQS_BITS-1:0] reqq_req_tid_st0;
wire [`REQS_BITS-1:0] reqq_req_tid_st0;
wire reqq_req_rw_st0;
wire [WORD_SIZE-1:0] reqq_req_byteen_st0;
`IGNORE_WARNINGS_BEGIN
wire [31:0] reqq_req_addr_st0;
wire [`WORD_ADDR_WIDTH-1:0] reqq_req_addr_st0;
`IGNORE_WARNINGS_END
wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0;
VX_cache_req_queue #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.REQQ_SIZE (REQQ_SIZE),
.CREQ_SIZE (CREQ_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) req_queue (
@@ -197,28 +201,28 @@ module VX_bank #(
.reset (reset),
// Enqueue
.reqq_push (reqq_push),
.bank_valids (core_req_valids),
.bank_valids (core_req_valid),
.bank_rw (core_req_rw),
.bank_byteen (core_req_byteen),
.bank_addr (core_req_addr),
.bank_writedata (core_req_data),
.bank_tag (core_req_tag),
.bank_mem_read (core_req_read),
.bank_mem_write (core_req_write),
.bank_tag (core_req_tag),
// Dequeue
.reqq_pop (reqq_pop),
.reqq_req_st0 (reqq_req_st0),
.reqq_req_tid_st0 (reqq_req_tid_st0),
.reqq_req_rw_st0 (reqq_req_rw_st0),
.reqq_req_byteen_st0 (reqq_req_byteen_st0),
.reqq_req_addr_st0 (reqq_req_addr_st0),
.reqq_req_writedata_st0(reqq_req_writeword_st0),
.reqq_req_tag_st0 (reqq_req_tag_st0),
.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
.reqq_empty (reqq_empty),
.reqq_full (reqq_full)
);
assign core_req_ready = ~reqq_full;
assign reqq_push = (| core_req_valids) && core_req_ready;
assign reqq_push = (| core_req_valid) && core_req_ready;
wire mrvq_pop;
wire mrvq_full;
@@ -226,11 +230,11 @@ module VX_bank #(
wire mrvq_valid_st0;
wire[`REQS_BITS-1:0] mrvq_tid_st0;
wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
wire [`BASE_ADDR_BITS-1:0] mrvq_wsel_st0;
wire [`WORD_SELECT_WIDTH-1:0] mrvq_wsel_st0;
wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0;
wire [`BYTE_EN_BITS-1:0] mrvq_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] mrvq_mem_write_st0;
wire mrvq_rw_st0;
wire [WORD_SIZE-1:0] mrvq_byteen_st0;
wire mrvq_is_snp_st0;
wire mrvq_pending_hazard_st1e;
@@ -239,8 +243,8 @@ module VX_bank #(
wire[`REQS_BITS-1:0] miss_add_tid;
wire[`REQ_TAG_WIDTH-1:0] miss_add_tag;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_read;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_write;
wire miss_add_rw;
wire[WORD_SIZE-1:0] miss_add_byteen;
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
wire is_fill_st2;
@@ -268,13 +272,11 @@ module VX_bank #(
end
end
wire mrvq_pop_unqual = mrvq_valid_st0;
wire dfpq_pop_unqual = !mrvq_pop_unqual && !dfpq_empty;
wire reqq_pop_unqual = !mrvq_stop && !mrvq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && reqq_req_st0 && !is_fill_st1[0] && !is_fill_in_pipe;
wire snrq_pop_unqual = !mrvq_stop && !reqq_pop_unqual && !reqq_pop_unqual && !mrvq_pop_unqual && !dfpq_pop_unqual && !snrq_empty;
assign mrvq_pop = mrvq_pop_unqual && !stall_bank_pipe && !recover_mrvq_state_st2;
assign dfpq_pop = dfpq_pop_unqual && !stall_bank_pipe;
assign reqq_pop = reqq_pop_unqual && !stall_bank_pipe;
@@ -283,7 +285,7 @@ module VX_bank #(
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
wire [`WORD_SELECT_ADDR_END:0] qual_wsel_st0;
wire [`WORD_SELECT_WIDTH-1:0] qual_wsel_st0;
wire qual_from_mrvq_st0;
wire [`WORD_WIDTH-1:0] qual_writeword_st0;
@@ -294,7 +296,7 @@ module VX_bank #(
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_WIDTH-1:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0];
@@ -307,24 +309,24 @@ module VX_bank #(
assign qual_addr_st0 = dfpq_pop_unqual ? dfpq_addr_st0 :
mrvq_pop_unqual ? mrvq_addr_st0 :
reqq_pop_unqual ? reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] :
reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] :
snrq_pop_unqual ? snrq_addr_st0 :
0;
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`BASE_ADDR_BITS-1:0] :
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 :
0;
assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), `BYTE_EN_BITS'(0), `BYTE_EN_BITS'(0), `REQS_BITS'(0)} :
assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} :
reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} :
snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} :
0;
assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 :
(mrvq_pop_unqual && (mrvq_mem_write_st0 != `BYTE_EN_NO)) ? 1 :
(reqq_pop_unqual && (reqq_req_mem_write_st0 != `BYTE_EN_NO)) ? 1 :
(mrvq_pop_unqual && mrvq_rw_st0) ? 1 :
(reqq_pop_unqual && reqq_req_rw_st0) ? 1 :
0;
assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 :
@@ -337,14 +339,14 @@ module VX_bank #(
assign qual_from_mrvq_st0 = mrvq_pop_unqual;
`DEBUG_BEGIN
`DEBUG_BLOCK(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0;
assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = qual_inst_meta_st0;
end
`DEBUG_END
)
VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_c0 (
.clk (clk),
.reset (reset),
@@ -357,7 +359,7 @@ module VX_bank #(
genvar i;
for (i = 1; i < STAGE_1_CYCLES; i++) begin
VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_cc (
.clk (clk),
.reset(reset),
@@ -369,16 +371,17 @@ module VX_bank #(
end
wire[`WORD_WIDTH-1:0] readword_st1e;
wire[`BANK_LINE_WIDTH-1:0] readdata_st1e;
wire[`BANK_LINE_WIDTH-1:0] readdata_st1e;
wire[`TAG_SELECT_BITS-1:0] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
wire[BANK_LINE_SIZE-1:0] dirtyb_st1e;
`DEBUG_BEGIN
wire [`REQ_TAG_WIDTH-1:0] tag_st1e;
wire [`REQS_BITS-1:0] tid_st1e;
`DEBUG_END
wire [`BYTE_EN_BITS-1:0] mem_read_st1e;
wire [`BYTE_EN_BITS-1:0] mem_write_st1e;
wire mem_rw_st1e;
wire [WORD_SIZE-1:0] mem_byteen_st1e;
wire fill_saw_dirty_st1e;
wire is_snp_st1e;
wire snp_to_mrvq_st1e;
@@ -392,12 +395,11 @@ module VX_bank #(
assign valid_st1e = valid_st1 [STAGE_1_CYCLES-1];
assign is_snp_st1e = is_snp_st1 [STAGE_1_CYCLES-1];
assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign {tag_st1e, mem_rw_st1e, mem_byteen_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign st2_pending_hazard_st1e = (miss_add_because_miss) && ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e)) || (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e)) || (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign mrvq_recover_ready_state_st1e = valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2 && (addr_st2 == addr_st1[STAGE_1_CYCLES-1]);
@@ -421,17 +423,17 @@ module VX_bank #(
.readaddr_st10(addr_st1[0][`LINE_SELECT_BITS-1:0]),
// Actual Read/Write
.valid_req_st1e(valid_st1e),
.writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e(wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]),
.valid_req_st1e (valid_st1e),
.writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e (wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e),
.mem_read_st1e (mem_read_st1e),
.mem_rw_st1e (mem_rw_st1e),
.mem_byteen_st1e (mem_byteen_st1e),
.is_snp_st1e (is_snp_st1e),
.is_snp_st1e (is_snp_st1e),
// Read Data
.readword_st1e (readword_st1e),
@@ -439,27 +441,28 @@ module VX_bank #(
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e),
.dirtyb_st1e (dirtyb_st1e),
.fill_saw_dirty_st1e (fill_saw_dirty_st1e),
.snp_to_mrvq_st1e (snp_to_mrvq_st1e),
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_tagid_st1e, debug_rw_st1e, debug_byteen_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
end
`DEBUG_END
)
wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1];
wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e;
wire valid_st2;
wire [`BASE_ADDR_BITS-1:0] wsel_st2;
wire [`WORD_SELECT_WIDTH-1:0] wsel_st2;
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2;
wire [`BANK_LINE_WIDTH-1:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire [BANK_LINE_SIZE-1:0] dirtyb_st2;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2;
wire [`TAG_SELECT_BITS-1:0] readtag_st2;
wire fill_saw_dirty_st2;
@@ -474,22 +477,21 @@ module VX_bank #(
wire recover_mrvq_state_st2;
VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH)
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(1'b0),
.in ({mrvq_recover_ready_state_st1e, from_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_recover_ready_state_st2 , from_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
.in ({mrvq_recover_ready_state_st1e, from_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, dirtyb_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_recover_ready_state_st2 , from_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , dirtyb_st2, inst_meta_st2 })
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2;
assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2;
end
`DEBUG_END
)
// Enqueue to miss reserv if it's a valid miss
assign miss_add_because_miss = valid_st2 && !is_snp_st2 && miss_st2;
@@ -509,14 +511,13 @@ module VX_bank #(
assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2;
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`BASE_ADDR_BITS-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_SELECT_WIDTH-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2;
assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2;
wire miss_add_is_snp = is_snp_st2;
wire miss_add_from_mrvq = valid_st2 && from_mrvq_st2 && !stall_bank_pipe;
assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == qual_addr_st0 );
assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1[STAGE_1_CYCLES-1]);
@@ -544,8 +545,8 @@ module VX_bank #(
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_tag (miss_add_tag),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_add_rw (miss_add_rw),
.miss_add_byteen (miss_add_byteen),
.miss_add_is_snp (miss_add_is_snp),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
@@ -564,8 +565,8 @@ module VX_bank #(
.miss_resrv_data_st0 (mrvq_writeword_st0),
.miss_resrv_tid_st0 (mrvq_tid_st0),
.miss_resrv_tag_st0 (mrvq_tag_st0),
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
.miss_resrv_mem_write_st0(mrvq_mem_write_st0),
.miss_resrv_rw_st0 (mrvq_rw_st0),
.miss_resrv_byteen_st0 (mrvq_byteen_st0),
.miss_resrv_is_snp_st0 (mrvq_is_snp_st0)
);
@@ -581,10 +582,12 @@ module VX_bank #(
assign cwbq_push = cwbq_push_unqual
&& !cwbq_full
&& (miss_add_mem_write == `BYTE_EN_NO)
&& (miss_add_rw == 0)
&& !(dwbq_push_stall
|| mrvq_push_stall
|| dram_fill_req_stall);
|| dram_fill_req_stall);
assign cwbq_pop = core_rsp_valid && core_rsp_ready;
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid;
@@ -605,10 +608,9 @@ module VX_bank #(
.empty (cwbq_empty),
.full (cwbq_full),
`UNUSED_PIN (size)
);
);
assign core_rsp_valid = !cwbq_empty;
assign cwbq_pop = core_rsp_valid && core_rsp_ready;
// Enqueue DRAM fill request
@@ -664,23 +666,22 @@ module VX_bank #(
|| mrvq_push_stall
|| dram_fill_req_stall);
wire [`BANK_LINE_WIDTH-1:0] dwbq_req_data = readdata_st2;
wire [`LINE_ADDR_WIDTH-1:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st2 = SNP_REQ_TAG_WIDTH'(miss_add_tag);
VX_generic_queue #(
.DATAW(1 + 1 + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH),
.DATAW(1 + 1 + BANK_LINE_SIZE + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH),
.SIZE(DWBQ_SIZE)
) dwb_queue (
.clk (clk),
.reset (reset),
.push (dwbq_push),
.data_in ({dwbq_is_dwb_in, dwbq_is_snp_in, dwbq_req_addr, dwbq_req_data, snrq_tag_st2}),
.data_in ({dwbq_is_dwb_in, dwbq_is_snp_in, dirtyb_st2, dwbq_req_addr, readdata_st2, snrq_tag_st2}),
.pop (dwbq_pop),
.data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
.data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_byteen, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
.empty (dwbq_empty),
.full (dwbq_full),
`UNUSED_PIN (size)
@@ -717,25 +718,25 @@ module VX_bank #(
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, dram_fill_req_addr);
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, dram_wb_req_addr, dram_wb_req_data);
$display("%t: bank%01d%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_wb_req_addr), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, dram_fill_rsp_addr, dram_fill_rsp_data);
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end
end
end else begin
always_ff @(posedge clk) begin
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
$display("%t: bank%01d%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end
end

81
hw/rtl/cache/VX_cache.v vendored
View File

@@ -18,7 +18,7 @@ module VX_cache #(
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
parameter CREQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 16,
// Dram Fill Rsp Queue Size
@@ -69,23 +69,24 @@ module VX_cache #(
input wire reset,
// Core request
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
output wire core_req_ready,
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready,
input wire core_rsp_ready,
// DRAM request
output wire dram_req_read,
output wire dram_req_write,
output wire dram_req_valid,
output wire dram_req_rw,
output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
@@ -122,22 +123,18 @@ module VX_cache #(
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready
);
`DEBUG_BEGIN
`DEBUG_BLOCK(
wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb;
wire[2:0] debug_core_req_rmask;
wire[4:0] debug_core_req_rd;
wire[`NW_BITS-1:0] debug_core_req_warp_num;
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rmask, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
end
`DEBUG_END
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;
)
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;
wire [NUM_BANKS-1:0] per_bank_core_req_ready;
@@ -155,6 +152,7 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_dram_wb_req_ready;
wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_wb_req_byteen;
wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr;
wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data;
@@ -226,18 +224,18 @@ module VX_cache #(
) cache_core_req_bank_sel (
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids (per_bank_valids)
.per_bank_valid (per_bank_valid)
);
genvar i;
generate
for (i = 0; i < NUM_BANKS; i++) begin
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_write;
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid;
wire [NUM_REQUESTS-1:0] curr_bank_core_req_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
wire curr_bank_core_rsp_valid;
wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid;
@@ -250,11 +248,12 @@ module VX_cache #(
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr;
wire curr_bank_dram_fill_rsp_ready;
wire curr_bank_dram_fill_req_valid;
wire curr_bank_dram_fill_req_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_fill_req_ready;
wire curr_bank_dram_wb_req_valid;
wire [BANK_LINE_SIZE-1:0] curr_bank_dram_wb_req_byteen;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_dram_wb_req_ready;
@@ -271,12 +270,12 @@ module VX_cache #(
wire curr_bank_core_req_ready;
// Core Req
assign curr_bank_core_req_valids = per_bank_valids[i] & {NUM_REQUESTS{core_req_ready}};
assign curr_bank_core_req_valid = per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}};
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_rw = core_req_rw;
assign curr_bank_core_req_byteen = core_req_byteen;
assign curr_bank_core_req_data = core_req_data;
assign curr_bank_core_req_tag = core_req_tag;
assign curr_bank_core_req_read = core_req_read;
assign curr_bank_core_req_write = core_req_write;
assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
// Core WB
@@ -308,10 +307,11 @@ module VX_cache #(
// Dram writeback request
assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid;
assign per_bank_dram_wb_req_byteen[i] = curr_bank_dram_wb_req_byteen;
if (NUM_BANKS == 1) begin
assign per_bank_dram_wb_req_addr[i] = curr_bank_dram_wb_req_addr;
end else begin
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
end
assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data;
assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i];
@@ -341,7 +341,7 @@ module VX_cache #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.CREQ_SIZE (CREQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
@@ -358,9 +358,9 @@ module VX_cache #(
.clk (clk),
.reset (reset),
// Core request
.core_req_valids (curr_bank_core_req_valids),
.core_req_read (curr_bank_core_req_read),
.core_req_write (curr_bank_core_req_write),
.core_req_valid (curr_bank_core_req_valid),
.core_req_rw (curr_bank_core_req_rw),
.core_req_byteen (curr_bank_core_req_byteen),
.core_req_addr (curr_bank_core_req_addr),
.core_req_data (curr_bank_core_req_data),
.core_req_tag (curr_bank_core_req_tag),
@@ -386,6 +386,7 @@ module VX_cache #(
// Dram writeback request
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
.dram_wb_req_byteen (curr_bank_dram_wb_req_byteen),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data),
.dram_wb_req_ready (curr_bank_dram_wb_req_ready),
@@ -418,11 +419,13 @@ module VX_cache #(
.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
.dram_fill_req_ready (dram_fill_req_ready),
.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
.per_bank_dram_wb_req_byteen (per_bank_dram_wb_req_byteen),
.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
.per_bank_dram_wb_req_ready (per_bank_dram_wb_req_ready),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_ready (dram_req_ready)

25
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -5,11 +5,11 @@
`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_REQ_TAG_WIDTH)
// data tid tag read write base addr is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS + 1)
// tag rw byteen tid
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// tag read write reqs
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS)
// data metadata word_sel is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `WORD_SELECT_WIDTH + 1)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)
@@ -27,36 +27,39 @@
`define OFFSET_ADDR_BITS `CLOG2(WORD_SIZE)
`define OFFSET_ADDR_START 0
`define OFFSET_ADDR_END (`OFFSET_ADDR_START+`OFFSET_ADDR_BITS-1)
`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
// Word select
`define WORD_SELECT_BITS `CLOG2(`BANK_LINE_WORDS)
`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
`define WORD_SELECT_ADDR_END (`WORD_SELECT_ADDR_START+`WORD_SELECT_BITS-1)
`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
// Bank select
`define BANK_SELECT_BITS `CLOG2(NUM_BANKS)
`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
`define BANK_SELECT_ADDR_END (`BANK_SELECT_ADDR_START+`BANK_SELECT_BITS-1)
`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
// Line select
`define LINE_SELECT_BITS `CLOG2(`BANK_LINE_COUNT)
`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
`define LINE_SELECT_ADDR_END (`LINE_SELECT_ADDR_START+`LINE_SELECT_BITS-1)
`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
// Tag select
`define TAG_SELECT_BITS (31-`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_END 31
`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START
`define WORD_SELECT_WIDTH `LOG2UP(`BANK_LINE_WORDS)
`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))
`define DRAM_ADDR_WIDTH (32-`CLOG2(BANK_LINE_SIZE))
`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS)
`define BANK_SELECT_ADDR_RNG (`BANK_SELECT_BITS+`WORD_SELECT_BITS-1):`WORD_SELECT_BITS
`define LINE_SELECT_ADDR_RNG `WORD_ADDR_WIDTH-1:(`BANK_SELECT_BITS + `WORD_SELECT_BITS)
`define TAG_LINE_ADDR_RNG `LINE_ADDR_WIDTH-1:`LINE_SELECT_BITS
`define BASE_ADDR_BITS (`WORD_SELECT_BITS+`OFFSET_ADDR_BITS)
@@ -69,8 +72,12 @@
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
`define BYTE_TO_WORD_ADDR(x, w) (32-`CLOG2(w))'(x >> `CLOG2(w))
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, `BANK_SELECT_BITS'(i), `BASE_ADDR_BITS'(0)}
`define LINE_TO_BYTE_ADDR0(x) {x, `BASE_ADDR_BITS'(0)}
`endif

12
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -13,24 +13,24 @@ module VX_cache_core_req_bank_sel #(
) (
input wire [NUM_REQUESTS-1:0] core_req_valid,
`IGNORE_WARNINGS_BEGIN
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
`IGNORE_WARNINGS_END
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid
);
integer i;
if (NUM_BANKS == 1) begin
always @(*) begin
per_bank_valids = 0;
per_bank_valid = 0;
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valids[0][i] = core_req_valid[i];
per_bank_valid[0][i] = core_req_valid[i];
end
end
end else begin
always @(*) begin
per_bank_valids = 0;
per_bank_valid = 0;
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valids[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
per_bank_valid[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
end
end
end

15
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -31,14 +31,13 @@ module VX_cache_core_rsp_merge #(
assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
wire [`BANK_BITS-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) sel_bank (
.valids(per_bank_core_rsp_valid),
.index (main_bank_index),
.found (found_bank)
`UNUSED_PIN (found)
);
integer i;
@@ -47,13 +46,8 @@ module VX_cache_core_rsp_merge #(
assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index];
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (found_bank
&& per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))
if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
@@ -66,11 +60,8 @@ module VX_cache_core_rsp_merge #(
end else begin
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (found_bank
&& per_bank_core_rsp_valid[i]
if (per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin

15
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View File

@@ -23,13 +23,15 @@ module VX_cache_dram_req_arb #(
// Writeback Request
input wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid,
input wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_wb_req_byteen,
input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr,
input wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data,
output wire [NUM_BANKS-1:0] per_bank_dram_wb_req_ready,
// Merged Request
output wire dram_req_read,
output wire dram_req_write,
output wire dram_req_valid,
output wire dram_req_rw,
output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
@@ -54,7 +56,7 @@ module VX_cache_dram_req_arb #(
.clk (clk),
.reset (reset),
.dram_req (dram_req_read),
.dram_req (dram_req_valid && ~dram_req_rw),
.dram_req_addr(dram_req_addr),
.pref_pop (pref_pop),
@@ -106,10 +108,9 @@ module VX_cache_dram_req_arb #(
assign per_bank_dram_wb_req_ready[i] = dram_req_ready && (dwb_bank == `BANK_BITS'(i));
end
wire dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid;
assign dram_req_write = dwb_valid && dram_req_valid;
assign dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_rw = dwb_valid;
assign dram_req_byteen = dwb_valid ? per_bank_dram_wb_req_byteen[dwb_bank] : {BANK_LINE_SIZE{1'b1}};
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
assign {dram_req_data} = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;

16
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -25,12 +25,12 @@ module VX_cache_miss_resrv #(
input wire miss_add,
input wire from_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel,
input wire[`WORD_SELECT_WIDTH-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write,
input wire miss_add_rw,
input wire[WORD_SIZE-1:0] miss_add_byteen,
input wire mrvq_init_ready_state,
input wire miss_add_is_snp,
output wire miss_resrv_full,
@@ -46,12 +46,12 @@ module VX_cache_miss_resrv #(
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0,
output wire[`WORD_SELECT_WIDTH-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0,
output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0,
output wire miss_resrv_rw_st0,
output wire[WORD_SIZE-1:0] miss_resrv_byteen_st0,
output wire miss_resrv_is_snp_st0
);
reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0];
@@ -93,7 +93,7 @@ module VX_cache_miss_resrv #(
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_rw_st0, miss_resrv_byteen_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && !from_mrvq && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
@@ -124,7 +124,7 @@ module VX_cache_miss_resrv #(
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= mrvq_init_ready_state;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel, miss_add_is_snp};
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_wsel, miss_add_is_snp};
tail_ptr <= tail_ptr + 1;
end else if (increment_head) begin
valid_table[head_ptr] <= 0;

90
hw/rtl/cache/VX_cache_req_queue.v vendored
View File

@@ -6,7 +6,7 @@ module VX_cache_req_queue #(
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 0,
// Core Request Queue Size
parameter REQQ_SIZE = 0,
parameter CREQ_SIZE = 0,
// core request tag size
parameter CORE_TAG_WIDTH = 0,
// size of tag id in core request tag
@@ -16,22 +16,22 @@ module VX_cache_req_queue #(
input wire reset,
// Enqueue Data
input wire reqq_push,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] bank_mem_read,
input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] bank_mem_write,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] bank_writedata,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] bank_tag,
input wire reqq_push,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0] bank_rw,
input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] bank_byteen,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] bank_writedata,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] bank_addr,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] bank_tag,
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`REQS_BITS-1:0] reqq_req_tid_st0,
output wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0,
output wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0,
output wire reqq_req_rw_st0,
output wire [WORD_SIZE-1:0] reqq_req_byteen_st0,
output wire [`WORD_ADDR_WIDTH-1:0] reqq_req_addr_st0,
output wire [`WORD_WIDTH-1:0] reqq_req_writedata_st0,
output wire [31:0] reqq_req_addr_st0,
output wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0,
// State Data
@@ -39,30 +39,26 @@ module VX_cache_req_queue #(
output wire reqq_full
);
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0][31:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] out_per_writedata;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] out_per_mem_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] out_per_mem_write;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] out_per_tag;
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0] out_per_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] out_per_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] out_per_writedata;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] out_per_tag;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0][31:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] use_per_writedata;
reg [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] use_per_mem_read;
reg [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] use_per_mem_write;
reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] use_per_tag;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0] use_per_rw;
reg [NUM_REQUESTS-1:0][WORD_SIZE-1:0] use_per_byteen;
reg [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] use_per_writedata;
reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] use_per_tag;
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0][31:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] qual_writedata;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] qual_mem_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] qual_mem_write;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] qual_tag;
`DEBUG_BEGIN
reg [NUM_REQUESTS-1:0] updated_valids;
`DEBUG_END
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0] qual_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] qual_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] qual_writedata;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] qual_tag;
wire o_empty;
@@ -73,15 +69,15 @@ module VX_cache_req_queue #(
wire pop_qual = !out_empty && use_empty;
VX_generic_queue #(
.DATAW($bits(bank_valids) + $bits(bank_addr) + $bits(bank_writedata) + $bits(bank_tag) + $bits(bank_mem_read) + $bits(bank_mem_write)),
.SIZE(REQQ_SIZE)
.DATAW($bits(bank_valids) + $bits(bank_addr) + $bits(bank_writedata) + $bits(bank_tag) + $bits(bank_rw) + $bits(bank_byteen)),
.SIZE(CREQ_SIZE)
) reqq_queue (
.clk (clk),
.reset (reset),
.push (push_qual),
.data_in ({bank_valids, bank_addr, bank_writedata, bank_tag, bank_mem_read, bank_mem_write}),
.data_in ({bank_valids, bank_rw, bank_byteen, bank_addr, bank_writedata, bank_tag}),
.pop (pop_qual),
.data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
.data_out ({out_per_valids, out_per_rw, out_per_byteen, out_per_addr, out_per_writedata, out_per_tag}),
.empty (o_empty),
.full (reqq_full),
`UNUSED_PIN (size)
@@ -93,8 +89,8 @@ module VX_cache_req_queue #(
assign qual_addr = use_per_addr;
assign qual_writedata = use_per_writedata;
assign qual_tag = use_per_tag;
assign qual_mem_read = use_per_mem_read;
assign qual_mem_write = use_per_mem_write;
assign qual_rw = use_per_rw;
assign qual_byteen = use_per_byteen;
wire[`REQS_BITS-1:0] qual_request_index;
wire qual_has_request;
@@ -110,6 +106,8 @@ module VX_cache_req_queue #(
assign reqq_empty = !qual_has_request;
assign reqq_req_st0 = qual_has_request;
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_rw_st0 = qual_rw[qual_request_index];
assign reqq_req_byteen_st0 = qual_byteen[qual_request_index];
assign reqq_req_addr_st0 = qual_addr[qual_request_index];
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
@@ -117,17 +115,17 @@ module VX_cache_req_queue #(
assign reqq_req_tag_st0 = qual_tag;
end else begin
assign reqq_req_tag_st0 = qual_tag[qual_request_index];
end
assign reqq_req_mem_read_st0 = qual_mem_read [qual_request_index];
assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index];
end
`DEBUG_BLOCK(
reg [NUM_REQUESTS-1:0] updated_valids;
always @(*) begin
updated_valids = qual_valids;
if (qual_has_request) begin
updated_valids[qual_request_index] = 0;
end
end
)
always @(posedge clk) begin
if (reset) begin
@@ -135,11 +133,11 @@ module VX_cache_req_queue #(
end else begin
if (pop_qual) begin
use_per_valids <= real_out_per_valids;
use_per_rw <= out_per_rw;
use_per_byteen <= out_per_byteen;
use_per_addr <= out_per_addr;
use_per_writedata <= out_per_writedata;
use_per_tag <= out_per_tag;
use_per_mem_read <= out_per_mem_read;
use_per_mem_write <= out_per_mem_write;
use_per_tag <= out_per_tag;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= 0;
end

126
hw/rtl/cache/VX_tag_data_access.v vendored
View File

@@ -35,10 +35,10 @@ module VX_tag_data_access #(
input wire[`WORD_WIDTH-1:0] writeword_st1e,
input wire[`BANK_LINE_WIDTH-1:0] writedata_st1e,
`IGNORE_WARNINGS_BEGIN
input wire[`WORD_SELECT_ADDR_END:0] writewsel_st1e,
input wire[`BYTE_EN_BITS-1:0] mem_write_st1e,
input wire[`BYTE_EN_BITS-1:0] mem_read_st1e,
`IGNORE_WARNINGS_BEGIN
input wire mem_rw_st1e,
input wire[WORD_SIZE-1:0] mem_byteen_st1e,
input wire[`WORD_SELECT_WIDTH-1:0] writewsel_st1e,
`IGNORE_WARNINGS_END
output wire[`WORD_WIDTH-1:0] readword_st1e,
@@ -46,6 +46,7 @@ module VX_tag_data_access #(
output wire[`TAG_SELECT_BITS-1:0] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e,
output wire[BANK_LINE_SIZE-1:0] dirtyb_st1e,
output wire fill_saw_dirty_st1e,
output wire snp_to_mrvq_st1e,
output wire mrvq_init_ready_state_st1e
@@ -53,16 +54,19 @@ module VX_tag_data_access #(
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[BANK_LINE_SIZE-1:0] read_dirtyb_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`BANK_LINE_WIDTH-1:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[BANK_LINE_SIZE-1:0] qual_read_dirtyb_st1;
wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1;
wire[`BANK_LINE_WIDTH-1:0] qual_read_data_st1;
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_st1e;
wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e;
wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e;
wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_write_enable;
@@ -90,8 +94,9 @@ module VX_tag_data_access #(
.stall_bank_pipe(stall_bank_pipe),
.read_addr (readaddr_st10),
.read_valid (qual_read_valid_st1),
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_dirtyb (qual_read_dirtyb_st1),
.read_tag (qual_read_tag_st1),
.read_data (qual_read_data_st1),
@@ -105,126 +110,56 @@ module VX_tag_data_access #(
);
VX_generic_register #(
.N(1 + 1 + `TAG_SELECT_BITS + `BANK_LINE_WIDTH),
.N(1 + 1 + BANK_LINE_SIZE + `TAG_SELECT_BITS + `BANK_LINE_WIDTH),
.PassThru(1)
) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(1'b0),
.in({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}),
.out({read_valid_st1c[0], read_dirty_st1c[0], read_tag_st1c[0], read_data_st1c[0]})
.in({qual_read_valid_st1, qual_read_dirty_st1, qual_read_dirtyb_st1, qual_read_tag_st1, qual_read_data_st1}),
.out({read_valid_st1c[0], read_dirty_st1c[0], read_dirtyb_st1c[0], read_tag_st1c[0], read_data_st1c[0]})
);
genvar i;
for (i = 1; i < STAGE_1_CYCLES-1; i++) begin
VX_generic_register #(
.N( 1 + 1 + `TAG_SELECT_BITS + `BANK_LINE_WIDTH)
.N( 1 + 1 + BANK_LINE_SIZE + `TAG_SELECT_BITS + `BANK_LINE_WIDTH)
) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(1'b0),
.in({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}),
.out({read_valid_st1c[i], read_dirty_st1c[i], read_tag_st1c[i], read_data_st1c[i]})
.in({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_dirtyb_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}),
.out({read_valid_st1c[i], read_dirty_st1c[i], read_dirtyb_st1c[i], read_tag_st1c[i], read_data_st1c[i]})
);
end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM
assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1];
assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1];
wire force_write = real_writefill;
wire should_write;
assign readword_st1e = use_read_data_st1e[writewsel_st1e * `WORD_WIDTH +: `WORD_WIDTH];
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we;
wire [`BANK_LINE_WIDTH-1:0] data_write;
if (WORD_SIZE == BANK_LINE_SIZE) begin
wire should_write = mem_rw_st1e
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
assign should_write = ((mem_write_st1e != `BYTE_EN_NO))
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write = (writewsel_st1e == `WORD_SELECT_WIDTH'(i)) && should_write && !real_writefill;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
assign we[i] = (force_write || (should_write && !real_writefill)) ? {WORD_SIZE{1'b1}} : {WORD_SIZE{1'b0}};
end
assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} :
normal_write ? mem_byteen_st1e:
{WORD_SIZE{1'b0}};
assign readword_st1e = use_read_data_st1e;
assign data_write = force_write ? writedata_st1e : writeword_st1e;
end else begin
wire[`OFFSET_ADDR_BITS-1:0] byte_select = writewsel_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_BITS-1:0] block_offset = writewsel_st1e[`WORD_SELECT_ADDR_RNG];
wire lb = valid_req_st1e && (mem_read_st1e == `BYTE_EN_LB);
wire lh = valid_req_st1e && (mem_read_st1e == `BYTE_EN_LH);
wire lbu = valid_req_st1e && (mem_read_st1e == `BYTE_EN_HB);
wire lhu = valid_req_st1e && (mem_read_st1e == `BYTE_EN_HH);
wire lw = valid_req_st1e && (mem_read_st1e == `BYTE_EN_LW);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire sb = valid_req_st1e && (mem_write_st1e == `BYTE_EN_LB);
wire sh = valid_req_st1e && (mem_write_st1e == `BYTE_EN_LH);
wire sw = valid_req_st1e && (mem_write_st1e == `BYTE_EN_LW);
wire [3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire [3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
assign should_write = (sw || sb || sh)
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
wire[`WORD_WIDTH-1:0] data_unmod = use_read_data_st1e[block_offset * 32 +: 32];
wire[`WORD_WIDTH-1:0] data_unQual = (b0 || lw) ? (data_unmod) :
b1 ? (data_unmod >> 8) :
b2 ? (data_unmod >> 16) :
(data_unmod >> 24);
wire[`WORD_WIDTH-1:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[`WORD_WIDTH-1:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[`WORD_WIDTH-1:0] lbu_data = (data_unQual & 32'hFF);
wire[`WORD_WIDTH-1:0] lhu_data = (data_unQual & 32'hFFFF);
wire[`WORD_WIDTH-1:0] lw_data = (data_unQual);
wire[`WORD_WIDTH-1:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readword_st1e = data_Qual;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write = (block_offset == `WORD_SELECT_BITS'(i)) && should_write && !real_writefill;
assign we[i] = (force_write) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
wire [`WORD_WIDTH-1:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} :
writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] sw_data = writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] use_write_dat = sb ? sb_data : sh ? sh_data : sw_data;
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = force_write ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : use_write_dat;
end
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e;
end
assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we;
@@ -242,7 +177,7 @@ module VX_tag_data_access #(
wire force_core_miss = (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e && !real_miss);
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
// The second term is basically saying always make an entry ready if there's already antoher entry waiting, even if you yourself see a miss
assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e || (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e);
@@ -250,6 +185,7 @@ module VX_tag_data_access #(
assign miss_st1e = real_miss || snoop_hit_no_pending || force_core_miss;
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;
assign dirtyb_st1e = use_read_dirtyb_st1e;
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;
assign fill_sent = miss_st1e;

40
hw/rtl/cache/VX_tag_data_structure.v vendored
View File

@@ -17,6 +17,7 @@ module VX_tag_data_structure #(
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire read_valid,
output wire read_dirty,
output wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] read_dirtyb,
output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire[`BANK_LINE_WIDTH-1:0] read_data,
@@ -30,35 +31,41 @@ module VX_tag_data_structure #(
);
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg valid [`BANK_LINE_COUNT-1:0];
reg dirty [`BANK_LINE_COUNT-1:0];
assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr];
assign read_tag = tag [read_addr];
assign read_data = data [read_addr];
assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr];
assign read_dirtyb = dirtyb [read_addr];
assign read_tag = tag [read_addr];
assign read_data = data [read_addr];
wire going_to_write = (| write_enable);
wire do_write = (| write_enable);
integer i;
integer i, j;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < `BANK_LINE_COUNT; i++) begin
valid[i] <= 0;
dirty[i] <= 0;
valid[i] <= 0;
dirty[i] <= 0;
dirtyb[i] <= 0;
end
end else if (!stall_bank_pipe) begin
if (going_to_write) begin
if (do_write) begin
valid[write_addr] <= 1;
tag [write_addr] <= tag_index;
if (write_fill) begin
dirty[write_addr] <= 0;
dirty[write_addr] <= 0;
dirtyb[write_addr] <= 0;
end else begin
dirty[write_addr] <= 1;
dirty[write_addr] <= 1;
dirtyb[write_addr] <= dirtyb[write_addr] | write_enable;
end
end else if (fill_sent) begin
dirty[write_addr] <= 0;
dirty[write_addr] <= 0;
dirtyb[write_addr] <= 0;
end
if (invalidate) begin
@@ -66,10 +73,11 @@ module VX_tag_data_structure #(
end
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * 8 +: 8];
if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * 8 +: 8];
if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * 8 +: 8];
if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * 8 +: 8];
for (j = 0; j < WORD_SIZE; j++) begin
if (write_enable[i][j]) begin
data[write_addr][i][j] <= write_data[i * `WORD_WIDTH + j * 8 +: 8];
end
end
end
end
end

14
hw/rtl/interfaces/VX_cache_core_req_if.v
View File

@@ -10,13 +10,13 @@ interface VX_cache_core_req_if #(
parameter CORE_TAG_ID_BITS = 0
) ();
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
wire core_req_ready;
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0] core_req_rw;
wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen;
wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
wire core_req_ready;
endinterface

5
hw/rtl/interfaces/VX_cache_dram_req_if.v
View File

@@ -9,8 +9,9 @@ interface VX_cache_dram_req_if #(
parameter DRAM_TAG_WIDTH = 1
) ();
wire dram_req_read;
wire dram_req_write;
wire dram_req_valid;
wire dram_req_rw;
wire [(DRAM_LINE_WIDTH/8)-1:0] dram_req_byteen;
wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr;
wire [DRAM_LINE_WIDTH-1:0] dram_req_data;
wire [DRAM_TAG_WIDTH-1:0] dram_req_tag;

2
hw/rtl/interfaces/VX_join_if.v
View File

@@ -7,7 +7,7 @@
interface VX_join_if ();
wire is_join;
wire [`NW_BITS-1:0] join_warp_num;
wire [`NW_BITS-1:0] join_warp_num;
endinterface

56
hw/rtl/libs/VX_indexable_queue.v Normal file
View File

@@ -0,0 +1,56 @@
`include "VX_define.vh"
module VX_indexable_queue #(
parameter DATAW,
parameter SIZE
) (
input wire clk,
input wire reset,
input wire [DATAW-1:0] write_data,
output wire [`LOG2UP(SIZE)-1:0] write_addr,
input wire push,
output wire full,
input wire pop,
input wire [`LOG2UP(SIZE)-1:0] read_addr,
output wire [DATAW-1:0] read_data
);
reg [DATAW-1:0] data [SIZE-1:0];
reg valid [SIZE-1:0];
reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;
wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a;
wire enqueue, dequeue, empty;
assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0];
assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0];
assign empty = (wr_ptr == rd_ptr);
assign full = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);
assign enqueue = push && ~full;
assign dequeue = ~empty && ~valid[rd_a]; // auto-remove when head is invalid
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 0;
wr_ptr <= 0;
end else begin
if (enqueue) begin
data[wr_a] <= write_data;
valid[wr_a] <= 1;
wr_ptr <= wr_ptr + 1;
end
if (dequeue) begin
rd_ptr <= rd_ptr + 1;
end
if (pop) begin
valid[read_addr] <= 0;
end
end
end
assign write_addr = wr_a;
assign read_data = data[read_addr];
endmodule

206
hw/simulate/ram.h
View File

@@ -3,24 +3,30 @@
#include <stdio.h>
#include <stdint.h>
class RAM;
uint32_t hti(char);
uint32_t hToI(const char *, uint32_t);
void loadHexImpl(const char *, RAM *);
class RAM {
private:
mutable uint8_t *mem_[(1 << 12)];
uint8_t *get(uint32_t address) const {
uint32_t block_addr = address >> 20;
uint32_t block_offset = address & 0x000FFFFF;
if (mem_[block_addr] == NULL) {
mem_[block_addr] = new uint8_t[(1 << 20)];
}
return mem_[block_addr] + block_offset;
}
public:
uint8_t *mem[1 << 12];
RAM() {
for (uint32_t i = 0; i < (1 << 12); i++)
mem[i] = NULL;
for (uint32_t i = 0; i < (1 << 12); i++) {
mem_[i] = NULL;
}
}
~RAM() {
for (uint32_t i = 0; i < (1 << 12); i++)
if (mem[i])
delete[] mem[i];
this->clear();
}
size_t size() const {
@@ -29,184 +35,30 @@ public:
void clear() {
for (uint32_t i = 0; i < (1 << 12); i++) {
if (mem[i]) {
delete mem[i];
mem[i] = NULL;
if (mem_[i]) {
delete mem_[i];
mem_[i] = NULL;
}
}
}
uint8_t *get(uint32_t address) {
if (mem[address >> 20] == NULL) {
uint8_t *ptr = new uint8_t[1024 * 1024];
for (uint32_t i = 0; i < 1024 * 1024; i += 4) {
ptr[i + 0] = 0x00;
ptr[i + 1] = 0x00;
ptr[i + 2] = 0x00;
ptr[i + 3] = 0x00;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address, uint32_t length, uint8_t *data) {
void read(uint32_t address, uint32_t length, uint8_t *data) const {
for (unsigned i = 0; i < length; i++) {
data[i] = (*this)[address + i];
data[i] = *this->get(address + i);
}
}
void write(uint32_t address, uint32_t length, uint8_t *data) {
void write(uint32_t address, uint32_t length, const uint8_t *data) {
for (unsigned i = 0; i < length; i++) {
(*this)[address + i] = data[i];
*this->get(address + i) = data[i];
}
}
void getBlock(uint32_t address, uint8_t *data) {
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t *data) {
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
}
void writeWord(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++) {
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++) {
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t &operator[](uint32_t address) {
uint8_t& operator[](uint32_t address) {
return *get(address);
}
};
// MEMORY UTILS
inline uint32_t hti(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
}
inline uint32_t hToI(const char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
const uint8_t& operator[](uint32_t address) const {
return *get(address);
}
return value;
}
inline void loadHexImpl(const char *path, RAM *mem) {
mem->clear();
FILE *fp = fopen(path, "r");
if (fp == 0) {
printf("Path not found %s\n", path);
return;
// std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t *)mem->get(0))[1] = 0xf1401073;
((uint32_t *)mem->get(0))[2] = 0x30101073;
((uint32_t *)mem->get(0))[3] = 0x800000b7;
((uint32_t *)mem->get(0))[4] = 0x000080e7;
((uint32_t *)mem->get(0x80000000))[0] = 0x00000097;
((uint32_t *)mem->get(0xb0000000))[0] = 0x01C02023;
// F00FFF10
((uint32_t *)mem->get(0xf00fff10))[0] = 0x12345678;
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char *content = new char[size];
fread(content, 1, size, fp);
int offset = 0;
char *line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI(line + 1, 2);
uint32_t nextAddr = hToI(line + 3, 4) + offset;
uint32_t key = hToI(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(mem->get(add)) = hToI(line + 9 + i * 2, 2);
}
break;
case 2:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 4;
break;
case 4:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}
if (content)
delete[] content;
}
};

139
hw/simulate/simulator.cpp
View File

@@ -1,5 +1,6 @@
#include "simulator.h"
#include <iostream>
#include <fstream>
#include <iomanip>
uint64_t timestamp = 0;
@@ -44,6 +45,90 @@ void Simulator::attach_ram(RAM* ram) {
dram_rsp_vec_.clear();
}
void Simulator::load_bin(const char* program_file) {
if (ram_ == nullptr)
return;
std::ifstream ifs(program_file);
if (!ifs) {
std::cout << "error: " << program_file << " not found" << std::endl;
}
ifs.seekg(0, ifs.end);
auto size = ifs.tellg();
std::vector<uint8_t> content(size);
ifs.seekg(0, ifs.beg);
ifs.read((char*)content.data(), size);
ram_->write(STARTUP_ADDR, size, content.data());
}
void Simulator::load_ihex(const char* program_file) {
if (ram_ == nullptr)
return;
auto hti = [&](char c)->uint32_t {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
};
auto hToI = [&](const char *c, uint32_t size)->uint32_t {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
}
return value;
};
std::ifstream ifs(program_file);
if (!ifs) {
std::cout << "error: " << program_file << " not found" << std::endl;
}
ifs.seekg(0, ifs.end);
uint32_t size = ifs.tellg();
std::vector<char> content(size);
ifs.seekg(0, ifs.beg);
ifs.read(content.data(), size);
int offset = 0;
char *line = content.data();
while (true) {
if (line[0] == ':') {
uint32_t byteCount = hToI(line + 1, 2);
uint32_t nextAddr = hToI(line + 3, 4) + offset;
uint32_t key = hToI(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
(*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2);
}
break;
case 2:
offset = hToI(line + 9, 4) << 4;
break;
case 4:
offset = hToI(line + 9, 4) << 16;
break;
default:
break;
}
}
while (*line != '\n' && size != 0) {
++line;
--size;
}
if (size <= 1)
break;
++line;
--size;
}
}
void Simulator::print_stats(std::ostream& out) {
out << std::left;
out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl;
@@ -71,9 +156,7 @@ void Simulator::dbus_driver() {
if ((dequeue_index != -1)
&& vortex_->dram_rsp_ready) {
vortex_->dram_rsp_valid = 1;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
vortex_->dram_rsp_data[i] = dram_rsp_vec_[dequeue_index].data[i];
}
memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
free(dram_rsp_vec_[dequeue_index].data);
dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
@@ -94,44 +177,40 @@ void Simulator::dbus_driver() {
// handle DRAM requests
if (!dram_stalled) {
if (vortex_->dram_req_read) {
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data = (unsigned*)malloc(GLOBAL_BLOCK_SIZE);
dram_req.tag = vortex_->dram_req_tag;
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
dram_rsp_vec_.push_back(dram_req);
}
if (vortex_->dram_req_write) {
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
if (vortex_->dram_req_valid) {
if (vortex_->dram_req_rw) {
uint64_t byteen = vortex_->dram_req_byteen;
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
uint8_t* data = (uint8_t*)(vortex_->dram_req_data);
for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
(*ram_)[base_addr + i] = data[i];
}
}
} else {
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
dram_req.tag = vortex_->dram_req_tag;
ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
dram_rsp_vec_.push_back(dram_req);
}
}
}
vortex_->dram_req_ready = ~dram_stalled;
}
void Simulator::io_driver() {
if (vortex_->io_req_write
if (vortex_->io_req_valid
&& vortex_->io_req_rw
&& vortex_->io_req_addr == IO_BUS_ADDR_COUT) {
uint32_t data_write = (uint32_t)vortex_->io_req_data;
char c = (char)data_write;
std::cout << c;
}
vortex_->io_req_ready = 1;
vortex_->io_rsp_valid = 01;
vortex_->io_rsp_valid = 0;
}
void Simulator::reset() {
@@ -251,4 +330,4 @@ bool Simulator::run() {
#endif
return (status == 1);
}
}

5
hw/simulate/simulator.h
View File

@@ -21,7 +21,7 @@
typedef struct {
int cycles_left;
unsigned *data;
uint8_t *data;
unsigned tag;
} dram_req_t;
@@ -31,6 +31,9 @@ public:
Simulator();
virtual ~Simulator();
void load_bin(const char* program_file);
void load_ihex(const char* program_file);
bool is_busy();
void reset();
void step();

39
hw/simulate/testbench.cpp
View File

@@ -58,20 +58,19 @@ int main(int argc, char **argv)
"../../benchmarks/riscv_tests/rv32um-p-remu.hex"
};
for (std::string s : tests) {
for (std::string test : tests) {
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
std::cerr << test << std::endl;
RAM ram;
loadHexImpl(s.c_str(), &ram);
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl;
std::cerr << DEFAULT;
passed = passed && curr;
}
@@ -79,37 +78,29 @@ int main(int argc, char **argv)
std::cerr << DEFAULT << "\n***************************************\n";
if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
if (!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
return !passed;
#else
char testing[] = "../../runtime/tests/simple/vx_simple_main.hex";
//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
char test[] = "../../runtime/tests/simple/vx_simple_main.hex";
//char test[] = "../../benchmarks/riscv_tests/rv32ui-p-lb.hex";
//char test[] = "../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char test[] = "../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
// const char *testing;
// if (argc >= 2) {
// testing = argv[1];
// } else {
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;
std::cerr << test << std::endl;
RAM ram;
loadHexImpl(testing, &ram);
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test);
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl;
return !curr;
return !curr;
#endif
}