adding dram writeenable support + scheduler bug fixes

driver/common/vx_utils.cpp

@@ -97,15 +97,11 @@ extern int vx_upload_kernel_file(vx_device_h device, const char* filename) {
     return -1;
   }
 
-  // get length of file:
+  // read file content
   ifs.seekg(0, ifs.end);
   auto size = ifs.tellg();
+  auto content = new char [size];   
   ifs.seekg(0, ifs.beg);
-
-  // allocate buffer 
-  auto content = new char [size];  
-
-  // read file content
   ifs.read(content, size);
 
   // upload

driver/rtlsim/Makefile

@@ -12,13 +12,13 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
 				  -DDBG_PRINT_DRAM        \
 				  -DDBG_PRINT_OPAE
 
-#DBG_PRINT=$(DBG_PRINT_FLAGS)
+DBG_PRINT=$(DBG_PRINT_FLAGS)
 
 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
-MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
+#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
 
-#DEBUG = 1
+DEBUG = 1
 
 CFLAGS += -fPIC
 

driver/rtlsim/vortex.cpp

@@ -143,7 +143,6 @@ public:
         return 0;
     }
 
-
 private:
 
     size_t mem_allocation_;     

driver/tests/basic/common.h

@@ -3,6 +3,6 @@
 
 #define DEV_MEM_SRC_ADDR 0x10000000
 #define DEV_MEM_DST_ADDR 0x20000000
-#define NUM_BLOCKS       16
+#define NUM_BLOCKS       64
 
 #endif