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Finished Cache Integration

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This commit is contained in:
felsabbagh3
2019-10-22 06:02:08 -04:00
parent b7af8c3f34
commit 9d8273afe4
21 changed files with 2317 additions and 16 deletions
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40
rtl/VX_dmem_controller.v
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@@ -3,7 +3,9 @@
module VX_dmem_controller (
input wire clk,
input wire reset,
// MEM-RAM
VX_dram_req_rsp_inter VX_dram_req_rsp,
// MEM-Processor
VX_dcache_request_inter VX_dcache_req,
VX_dcache_response_inter VX_dcache_rsp
@@ -14,7 +16,10 @@ module VX_dmem_controller (
wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}};
wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}};
// Cache don't understand
wire initial_request = (|cache_driver_in_valid);
wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE);
@@ -25,8 +30,10 @@ module VX_dmem_controller (
wire[`NT_M1:0][31:0] cache_driver_out_data;
wire[`NT_M1:0][31:0] sm_driver_out_data;
wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
wire delay;
wire sm_delay;
wire cache_delay;
VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
@@ -37,15 +44,34 @@ module VX_dmem_controller (
.mem_read (cache_driver_in_mem_read),
.mem_write (cache_driver_in_mem_write),
.out_valid (cache_driver_out_valid),
.out_data (cache_driver_out_data),
.stall (delay)
.out_data (sm_driver_out_data),
.stall (sm_delay)
);
VX_d_cache dcache(
.clk (clk),
.rst (reset),
.i_p_valid (cache_driver_in_valid),
.i_p_addr (cache_driver_in_address),
.i_p_initial_request(),
.i_p_writedata (cache_driver_in_data),
.i_p_read_or_write (read_or_write),
.o_p_readdata (cache_driver_out_data),
.o_p_readdata_valid (),
.o_p_waitrequest (cache_delay),
.o_m_addr (VX_dram_req_rsp.o_m_addr),
.o_m_valid (VX_dram_req_rsp.o_m_valid),
.o_m_writedata (VX_dram_req_rsp.o_m_writedata),
.o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write),
.i_m_readdata (VX_dram_req_rsp.i_m_readdata),
.i_m_ready (VX_dram_req_rsp.i_m_ready)
);
assign VX_dcache_rsp.in_cache_driver_out_data = cache_driver_out_data;
assign VX_dcache_rsp.delay = delay;
assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data;
assign VX_dcache_rsp.delay = sm_delay || cache_delay;
endmodule