From 9cf5a29917aed7a0c8fe95b49f559748a55c0abe Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Fri, 17 Feb 2023 18:31:29 -0800
Subject: [PATCH] simx: add cycle and core id to load/store memory debug trace

---
 sim/simx/execute.cpp | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/sim/simx/execute.cpp b/sim/simx/execute.cpp
index fee169ba..776daa4d 100644
--- a/sim/simx/execute.cpp
+++ b/sim/simx/execute.cpp
@@ -690,8 +690,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         uint64_t mem_addr = rsdata[t][0].i + immsrc;         
         uint64_t mem_data = 0;
         core_->dcache_read(&mem_data, mem_addr, mem_bytes);
-        trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});        
-        DP(4, "LOAD MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes);
+        trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
+        DP(1, "LOAD MEM: CYCLE=" << SimPlatform::instance().cycles()
+              << ", CORE=" << core_->id()
+              << ", THREAD=" << t
+              << ", ADDRESS=0x" << std::hex << mem_addr
+              << ", DATA=0x" << mem_data << std::dec
+              << ", BYTES=" << mem_bytes);
         switch (func3) {
         case 0:
           // RV32I: LB
@@ -731,7 +736,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           core_->dcache_read(&mem_data, mem_addr, 4);
           Word *result_ptr = (Word *)(vd.data() + i);
           *result_ptr = mem_data;
-          DP(4, "LOAD MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4);        
+          DP(1, "LOAD MEM: CYCLE=" << SimPlatform::instance().cycles()
+                << ", CORE=" << core_->id()
+                << ", VLEN=" << vl_
+                << ", VID=" << i
+                << ", ADDRESS=0x" << std::hex << mem_addr
+                << ", DATA=0x" << mem_data << std::dec
+                << ", BYTES=" << 4);
         }
         break;
       } 
@@ -762,7 +773,12 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           mem_data &= mask;
         }
         trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});        
-        DP(4, "STORE MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes);
+        DP(1, "STORE MEM: CYCLE=" << SimPlatform::instance().cycles()
+              << ", CORE=" << core_->id()
+              << ", THREAD=" << t
+              << ", ADDRESS=0x" << std::hex << mem_addr
+              << ", DATA=0x" << mem_data << std::dec
+              << ", BYTES=" << mem_bytes);
         switch (func3) {
         case 0:
         case 1:
@@ -782,7 +798,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           // store word and unit strided (not checking for unit stride)          
           uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i);
           core_->dcache_write(&mem_data, mem_addr, 4);
-          DP(4, "STORE MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4);
+          DP(1, "STORE MEM: CYCLE=" << SimPlatform::instance().cycles()
+                << ", CORE=" << core_->id()
+                << ", VLEN=" << vl_
+                << ", VID=" << i
+                << ", ADDRESS=0x" << std::hex << mem_addr
+                << ", DATA=0x" << mem_data << std::dec
+                << ", BYTES=" << 4);
           break;
         } 
         default: