diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index e0b728b1..31285edc 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -269,15 +269,9 @@ // DRAM request data bits `define IDRAM_LINE_WIDTH (`ICACHE_LINE_SIZE * 8) -// DRAM request address bits -`define IDRAM_ADDR_WIDTH (32 - `CLOG2(`ICACHE_LINE_SIZE)) - // DRAM byte enable bits `define IDRAM_BYTEEN_WIDTH `ICACHE_LINE_SIZE -// DRAM request tag bits -`define IDRAM_TAG_WIDTH `IDRAM_ADDR_WIDTH - // Core request size `define INUM_REQUESTS 1 @@ -308,7 +302,7 @@ `define DDRAM_BYTEEN_WIDTH `DCACHE_LINE_SIZE // DRAM request tag bits -`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH +`define DDRAM_TAG_WIDTH `LOG2UP(`DNUM_BANKS) // Core request size `define DNUM_REQUESTS `NUM_THREADS @@ -324,17 +318,12 @@ // Word size in bytes `define SWORD_SIZE 4 +// bank address offset `define SBANK_ADDR_OFFSET `CLOG2(`STACK_SIZE / `SCACHE_LINE_SIZE) // Core request size `define SNUM_REQUESTS `NUM_THREADS -// DRAM request address bits -`define SDRAM_ADDR_WIDTH (32 - `CLOG2(`SCACHE_LINE_SIZE)) - -// DRAM request tag bits -`define SDRAM_TAG_WIDTH `SDRAM_ADDR_WIDTH - // Core request size `define SNUM_REQUESTS `NUM_THREADS @@ -362,7 +351,7 @@ `define L2DRAM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE // DRAM request tag bits -`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`XDRAM_TAG_WIDTH+`CLOG2(`NUM_CORES))) +`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `LOG2UP(`L2NUM_BANKS) : (`XDRAM_TAG_WIDTH+`CLOG2(`NUM_CORES))) ////////////////////////// L3cache Configurable Knobs ///////////////////////// @@ -388,7 +377,7 @@ `define L3DRAM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE // DRAM request tag bits -`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : (`L2DRAM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS))) +`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `LOG2UP(`L3NUM_BANKS) : (`L2DRAM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS))) /////////////////////////////////////////////////////////////////////////////// diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index b6d94d7c..86a397fe 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -84,7 +84,7 @@ module VX_mem_unit # ( VX_cache #( .CACHE_ID (`ICACHE_ID), .CACHE_SIZE (`ICACHE_SIZE), - .CACHE_LINE_SIZE (`ICACHE_LINE_SIZE), + .CACHE_LINE_SIZE (`ICACHE_LINE_SIZE), .NUM_BANKS (`INUM_BANKS), .WORD_SIZE (`IWORD_SIZE), .NUM_REQS (`INUM_REQUESTS), @@ -97,7 +97,7 @@ module VX_mem_unit # ( .WRITE_ENABLE (0), .CORE_TAG_WIDTH (`ICORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS), - .DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH) + .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH) ) icache ( `SCOPE_BIND_VX_mem_unit_icache @@ -142,7 +142,7 @@ module VX_mem_unit # ( VX_cache #( .CACHE_ID (`DCACHE_ID), .CACHE_SIZE (`DCACHE_SIZE), - .CACHE_LINE_SIZE (`DCACHE_LINE_SIZE), + .CACHE_LINE_SIZE (`DCACHE_LINE_SIZE), .NUM_BANKS (`DNUM_BANKS), .WORD_SIZE (`DWORD_SIZE), .NUM_REQS (`DNUM_REQUESTS), @@ -215,7 +215,6 @@ module VX_mem_unit # ( .WRITE_ENABLE (1), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS), - .DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH), .BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET) ) smem ( `SCOPE_BIND_VX_mem_unit_smem diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 5770eb4a..b3874b22 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -83,8 +83,7 @@ module VX_bank #( input wire dram_req_ready, // DRAM response - input wire dram_rsp_valid, - input wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr, + input wire dram_rsp_valid, input wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data, output wire dram_rsp_ready ); @@ -110,7 +109,6 @@ module VX_bank #( wire drsq_pop; wire drsq_empty; - wire [`LINE_ADDR_WIDTH-1:0] drsq_addr_st0; wire [`CACHE_LINE_WIDTH-1:0] drsq_filldata_st0; wire drsq_push = dram_rsp_valid && dram_rsp_ready; @@ -120,7 +118,7 @@ module VX_bank #( assign dram_rsp_ready = !drsq_full; VX_fifo_queue #( - .DATAW (`LINE_ADDR_WIDTH + $bits(dram_rsp_data)), + .DATAW ($bits(dram_rsp_data)), .SIZE (DRSQ_SIZE), .BUFFERED (1), .FASTRAM (1) @@ -129,18 +127,16 @@ module VX_bank #( .reset (reset), .push (drsq_push), .pop (drsq_pop), - .data_in ({dram_rsp_addr, dram_rsp_data}), - .data_out({drsq_addr_st0, drsq_filldata_st0}), + .data_in (dram_rsp_data), + .data_out(drsq_filldata_st0), .empty (drsq_empty), .full (drsq_full), `UNUSED_PIN (size) ); end else begin `UNUSED_VAR (dram_rsp_valid) - `UNUSED_VAR (dram_rsp_addr) `UNUSED_VAR (dram_rsp_data) assign drsq_empty = 1; - assign drsq_addr_st0 = 0; assign drsq_filldata_st0 = 0; assign dram_rsp_ready = 0; end @@ -312,9 +308,7 @@ module VX_bank #( assign valid_st0 = drsq_pop || mshr_pop || creq_pop; - assign addr_st0 = mshr_pop_unqual ? mshr_addr_st0 : - drsq_pop_unqual ? drsq_addr_st0 : - creq_addr_st0; + assign addr_st0 = creq_pop_unqual ? creq_addr_st0 : mshr_addr_st0; if (`WORD_SELECT_BITS != 0) begin assign wsel_st0 = creq_pop_unqual ? creq_wsel_st0 : mshr_wsel_st0; @@ -423,7 +417,7 @@ if (DRAM_ENABLE) begin assign core_req_hit_st1 = !is_fill_st1 && !miss_st1 && !force_miss_st1; - assign incoming_fill_st1 = !drsq_empty && (addr_st1 == drsq_addr_st0); + assign incoming_fill_st1 = !drsq_empty && (addr_st1 == mshr_addr_st0); wire do_fill_req_st1 = miss_st1 && !(WRITE_THROUGH && mem_rw_st1) @@ -583,7 +577,7 @@ end && !crsq_push_stall && !dreq_push_stall; - wire incoming_fill_qual_st2 = (!drsq_empty && (addr_st2 == drsq_addr_st0)) || incoming_fill_st2; + wire incoming_fill_qual_st2 = (!drsq_empty && (addr_st2 == mshr_addr_st0)) || incoming_fill_st2; if (DRAM_ENABLE) begin @@ -594,10 +588,7 @@ end // push missed requests as 'ready' if it was a forced miss but actually had a hit // or the fill request is comming for this block - wire mshr_init_ready_state_st2 = valid_st2 && (!miss_st2 || incoming_fill_qual_st2); - - // use dram rsp or core req address to lookup the mshr - wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = drsq_pop_unqual ? drsq_addr_st0 : creq_addr_st0; + wire mshr_init_ready_state_st2 = valid_st2 && (!miss_st2 || incoming_fill_qual_st2); VX_miss_resrv #( .BANK_ID (BANK_ID), @@ -630,7 +621,7 @@ end // lookup .lookup_ready (update_ready_st0), - .lookup_addr (lookup_addr), + .lookup_addr (addr_st0), .lookup_match (mshr_pending_hazard_unqual_st0), // schedule diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 03cf8071..f1024d74 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -42,7 +42,7 @@ module VX_cache #( parameter CORE_TAG_ID_BITS = 0, // dram request tag size - parameter DRAM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)), + parameter DRAM_TAG_WIDTH = `LOG2UP(NUM_BANKS), // bank offset from beginning of index range parameter BANK_ADDR_OFFSET = 0 @@ -89,7 +89,6 @@ module VX_cache #( ); `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) - `UNUSED_VAR (dram_rsp_tag) wire [NUM_BANKS-1:0] per_bank_core_req_valid; wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid; @@ -108,9 +107,9 @@ module VX_cache #( wire [NUM_BANKS-1:0] per_bank_dram_req_valid; wire [NUM_BANKS-1:0] per_bank_dram_req_rw; - wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_dram_req_byteen; + wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_dram_req_byteen; wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_req_addr; - wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_dram_req_data; + wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_dram_req_data; wire [NUM_BANKS-1:0] per_bank_dram_req_ready; wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready; @@ -154,11 +153,11 @@ module VX_cache #( .per_bank_core_req_ready (per_bank_core_req_ready) ); - assign dram_req_tag = dram_req_addr; if (NUM_BANKS == 1) begin + `UNUSED_VAR (dram_rsp_tag) assign dram_rsp_ready = per_bank_dram_rsp_ready; end else begin - assign dram_rsp_ready = per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag)]; + assign dram_rsp_ready = per_bank_dram_rsp_ready[dram_rsp_tag]; end for (genvar i = 0; i < NUM_BANKS; i++) begin @@ -186,7 +185,6 @@ module VX_cache #( wire curr_bank_dram_rsp_valid; wire [`CACHE_LINE_WIDTH-1:0] curr_bank_dram_rsp_data; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_rsp_addr; wire curr_bank_dram_rsp_ready; // Core Req @@ -221,10 +219,8 @@ module VX_cache #( // DRAM response if (NUM_BANKS == 1) begin assign curr_bank_dram_rsp_valid = dram_rsp_valid; - assign curr_bank_dram_rsp_addr = dram_rsp_tag; end else begin - assign curr_bank_dram_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i); - assign curr_bank_dram_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag); + assign curr_bank_dram_rsp_valid = dram_rsp_valid && (dram_rsp_tag == i); end assign curr_bank_dram_rsp_data = dram_rsp_data; assign per_bank_dram_rsp_ready[i] = curr_bank_dram_rsp_ready; @@ -289,7 +285,6 @@ module VX_cache #( // DRAM response .dram_rsp_valid (curr_bank_dram_rsp_valid), .dram_rsp_data (curr_bank_dram_rsp_data), - .dram_rsp_addr (curr_bank_dram_rsp_addr), .dram_rsp_ready (curr_bank_dram_rsp_ready) ); end @@ -315,14 +310,14 @@ module VX_cache #( ); if (DRAM_ENABLE) begin - wire [NUM_BANKS-1:0][(`DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in; + wire [NUM_BANKS-1:0][(DRAM_TAG_WIDTH + `DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in; for (genvar i = 0; i < NUM_BANKS; i++) begin - assign data_in[i] = {per_bank_dram_req_addr[i], per_bank_dram_req_rw[i], per_bank_dram_req_byteen[i], per_bank_dram_req_data[i]}; + assign data_in[i] = {DRAM_TAG_WIDTH'(i), per_bank_dram_req_addr[i], per_bank_dram_req_rw[i], per_bank_dram_req_byteen[i], per_bank_dram_req_data[i]}; end VX_stream_arbiter #( .NUM_REQS (NUM_BANKS), - .DATAW (`DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), + .DATAW (DRAM_TAG_WIDTH + `DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), .BUFFERED (1) ) dram_req_arb ( .clk (clk), @@ -331,7 +326,7 @@ module VX_cache #( .data_in (data_in), .ready_in (per_bank_dram_req_ready), .valid_out (dram_req_valid), - .data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}), + .data_out ({dram_req_tag, dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}), .ready_out (dram_req_ready) ); end else begin @@ -346,6 +341,7 @@ module VX_cache #( assign dram_req_byteen = 0; assign dram_req_addr = 0; assign dram_req_data = 0; + assign dram_req_tag = 0; `UNUSED_VAR (dram_req_ready) end diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index 8f625e22..34ecdf50 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -50,7 +50,6 @@ module VX_tag_access #( wire do_fill; wire do_write; - wire do_invalidate; wire [`TAG_SELECT_BITS-1:0] addrtag = `LINE_TAG_ADDR(addr_in); wire [`LINE_SELECT_BITS-1:0] addrline = addr_in [`LINE_SELECT_BITS-1:0]; @@ -73,7 +72,6 @@ module VX_tag_access #( .do_fill (do_fill), .do_write (do_write), - .invalidate (do_invalidate), .write_tag (addrtag) ); @@ -92,8 +90,6 @@ module VX_tag_access #( && is_fill_in && !stall; - assign do_invalidate = 0; - assign miss_out = valid_in && !tags_match && !is_fill_in; diff --git a/hw/rtl/cache/VX_tag_store.v b/hw/rtl/cache/VX_tag_store.v index 6965b104..b0078a75 100644 --- a/hw/rtl/cache/VX_tag_store.v +++ b/hw/rtl/cache/VX_tag_store.v @@ -19,7 +19,6 @@ module VX_tag_store #( input wire do_fill, input wire do_write, - input wire invalidate, input wire[`TAG_SELECT_BITS-1:0] write_tag, output wire[`TAG_SELECT_BITS-1:0] read_tag, @@ -41,8 +40,6 @@ module VX_tag_store #( dirty[addr] <= 0; end else if (do_write) begin dirty[addr] <= 1; - end else if (invalidate) begin - valid[addr] <= 0; end end end