minor update
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@@ -283,7 +283,7 @@
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`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH
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`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH
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`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
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`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
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`define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH
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`define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH
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`define VX_CORE_TAG_WIDTH `DCORE_TAG_WIDTH
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`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
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`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)}
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`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)}
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@@ -47,13 +47,13 @@ module Vortex_Cluster #(
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output wire [3:0] io_req_byteen,
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output wire [3:0] io_req_byteen,
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output wire [29:0] io_req_addr,
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output wire [29:0] io_req_addr,
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output wire [31:0] io_req_data,
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output wire [31:0] io_req_data,
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output wire [`DCORE_TAG_WIDTH-1:0] io_req_tag,
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output wire [`L2CORE_TAG_WIDTH-1:0] io_req_tag,
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input wire io_req_ready,
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input wire io_req_ready,
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// I/O response
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// I/O response
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input wire io_rsp_valid,
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input wire io_rsp_valid,
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input wire [31:0] io_rsp_data,
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input wire [31:0] io_rsp_data,
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input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
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input wire [`L2CORE_TAG_WIDTH-1:0] io_rsp_tag,
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output wire io_rsp_ready,
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output wire io_rsp_ready,
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// Status
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// Status
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@@ -180,7 +180,7 @@ module Vortex_Cluster #(
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end
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end
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VX_mem_arb #(
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VX_mem_arb #(
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.NUM_REQUESTS (`NUM_CLUSTERS),
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.NUM_REQUESTS (`NUM_CORES),
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.WORD_SIZE (4),
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.WORD_SIZE (4),
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.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
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.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
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.TAG_OUT_WIDTH (`L2CORE_TAG_WIDTH)
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.TAG_OUT_WIDTH (`L2CORE_TAG_WIDTH)
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