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Made the cache module configurable for multi-instantiation

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This commit is contained in:
felsabbagh3
2020-03-07 00:49:40 -08:00
parent fb23812e95
commit 9bf0add937
22 changed files with 1209 additions and 493 deletions
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8
rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
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@@ -6,7 +6,11 @@
`define VX_GPU_DRAM_DCACHE_REQ
interface VX_gpu_dcache_dram_req_inter ();
interface VX_gpu_dcache_dram_req_inter
#(
parameter BANK_LINE_SIZE_WORDS = 2
)
();
// DRAM Request
wire dram_req;
@@ -14,7 +18,7 @@ interface VX_gpu_dcache_dram_req_inter ();
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [31:0] dram_req_size;
wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data;
wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_req_data;
// Snoop
wire dram_because_of_snp;

8
rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
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@@ -7,11 +7,15 @@
`define VX_GPU_DRAM_DCACHE_RES
interface VX_gpu_dcache_dram_res_inter ();
interface VX_gpu_dcache_dram_res_inter
#(
parameter BANK_LINE_SIZE_WORDS = 2
)
();
// DRAM Rsponse
wire dram_fill_rsp;
wire [31:0] dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data;
wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_fill_rsp_data;
endinterface

12
rtl/interfaces/VX_gpu_dcache_req_inter.v
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@@ -6,12 +6,16 @@
`define VX_GPU_DCACHE_REQ
interface VX_gpu_dcache_req_inter ();
interface VX_gpu_dcache_req_inter
#(
parameter NUMBER_REQUESTS = 32
)
();
// Core Request
wire [`NUMBER_REQUESTS-1:0] core_req_valid;
wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr;
wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata;
wire [NUMBER_REQUESTS-1:0] core_req_valid;
wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr;
wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata;
wire [2:0] core_req_mem_read;
wire [2:0] core_req_mem_write;
wire [4:0] core_req_rd;

10
rtl/interfaces/VX_gpu_dcache_res_inter.v
View File

@@ -6,14 +6,18 @@
`define VX_GPU_DCACHE_RES
interface VX_gpu_dcache_res_inter ();
interface VX_gpu_dcache_res_inter
#(
parameter NUMBER_REQUESTS = 32
)
();
// Cache WB
wire [`NUMBER_REQUESTS-1:0] core_wb_valid;
wire [NUMBER_REQUESTS-1:0] core_wb_valid;
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [`NW_M1:0] core_wb_warp_num;
wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata;
// Cache Full
wire delay_req;